HEMT Gate Etching With Self-Formed Spacer Leakage Control
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Solution Overview
Problem
The surface of P-type group III-V gates in high electron mobility transistors is often damaged during the etching process, leading to leakage current issues, and existing methods require additional masking steps and wet etching processes.
Innovation Solution
A method involving the use of by-products formed during dry etching as a mask to etch the P-type group III-V compound material layer, eliminating the need for an extra mask and wet etching, and incorporating a metal compound layer with reduced width to prevent damage and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal compound layer width is the same as the P-type group III-V gate width, then the gate surface is fully protected during etching, but leakage current is generated under the gate
Solution Approach 1:
The metal compound layer is designed with non-uniform width: wider at the etching stage to protect the gate surface, then reduced to a narrower width in the final structure to prevent leakage current. This local variation in dimensional quality resolves the contradiction between protection and leakage prevention.
2Reliability
If additional masking steps and wet etching are used to protect the gate, then gate damage is prevented, but the fabrication process complexity increases
Solution Approach 1:
The metal compound layer serves dual functions: it acts as both the protective element during etching and as the final gate structure component. The layer protects the gate during fabrication through its own structural presence, then is precisely etched back to the required width, eliminating the need for separate masking and wet etching steps.
Solution Approach 2:
The metal compound layer performs multiple functions: (1) serves as the gate structure material, (2) acts as a self-mask during etching to define gate width, and (3) protects the underlying gate surface during processing. This multi-functionality simplifies the overall fabrication process by consolidating multiple steps into one integrated approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach protects the P-type group III-V gate surface, reduces leakage current, and simplifies the fabrication process by eliminating the need for wet etching and additional masking, while allowing for precise control of the gate width and threshold voltage modulation.
Implementation Method 1
a dry etching process is performed to etch the hard mask material layer and the metal compound material layer
Implementation Method 2
a spacer generated by by-products surrounds the patterned photoresist, the hard mask and the metal compound layer, and the by-products are formed during the dry etching process
Implementation Method 3
the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a second mask
Data Source
AI summary
A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.