HEMT Gate Stack Heterostructure for Low Leakage and Stable Threshold
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Solution Overview
Problem
Existing semiconductor structures face issues with increased gate-to-channel leakage current due to thin gate oxides, leading to negative shifts in threshold voltage and leak paths, especially in high electron mobility transistors (HEMTs), and high-k dielectrics result in bulk and interface traps, limiting electron mobility and device performance.
Innovation Solution
A semiconductor structure with a back-end device, such as a HEMT, incorporating a two-dimensional electron gas (2 DEG) region that maintains good interfacial quality between the channel layer and gate dielectric, formed using a heterostructure of different metal oxide materials to reduce interface traps and enhance electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If high-k dielectrics are used as gate dielectric, then gate-to-channel leakage current is reduced, but bulk and interface traps increase leading to negative threshold voltage shift and reduced electron mobility
Solution Approach 1:
The patent introduces an intermediary layer (cladding layer or interface layer) between the high-k gate dielectric and the channel layer. This intermediary layer acts as a mediator that prevents direct interaction between the high-k dielectric and channel, thereby reducing interface traps and preventing negative threshold voltage shift while maintaining the low leakage current benefit of high-k dielectrics
Solution Approach 2:
The patent employs composite gate dielectric structures combining high-k dielectric materials with other materials (such as silicon oxide or silicon nitride) to create a multi-layered gate stack. This composite structure leverages the low leakage properties of high-k dielectrics while using the other materials to passivate interface traps and stabilize threshold voltage
2Productivity
If gate oxide thickness is reduced to increase functional density, then more devices can be integrated per chip area, but gate-to-channel leakage current increases and threshold voltage control deteriorates
Solution Approach 1:
The patent uses composite gate dielectric structures with multiple layers having different dielectric constants and properties. This allows achieving equivalent capacitance with greater total thickness, thereby maintaining device density while reducing leakage current and improving threshold voltage control
Solution Approach 2:
The patent introduces intermediary layers between the gate dielectric and channel that prevent direct interaction and reduce leakage paths, enabling thinner effective gate oxide while maintaining control over threshold voltage and reducing gate-to-channel leakage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 2 DEG region improves electron mobility and reduces interface traps, enhancing bias stress reliability and controlling threshold voltage, thereby improving the performance of high electron mobility transistors.
Implementation Method 1
incorporating a two-dimensional electron gas (2 DEG) region that maintains good interfacial quality between the channel layer and gate dielectric, formed using a heterostructure of different metal oxide materials to reduce interface traps and enhance electron mobility
Implementation Method 2
A semiconductor structure with a back-end device, such as a HEMT, incorporating a two-dimensional electron gas (2 DEG) region that maintains good interfacial quality between the channel layer and gate dielectric
Data Source
AI summary
A semiconductor structure includes an interconnect structure over a substrate and a transistor embedded in the interconnect structure. The transistor includes at least one gate layer, a gate dielectric layer extending along the at least one gate layer, a channel layer extending along the gate dielectric layer, a heterostructure interposed between the gate dielectric layer and the channel layer, and source/drain vias connected to the channel layer. The heterostructure includes a two-dimensional electron gas region acting as a part of a channel of the transistor.