HEMT Gate Stack Patterning for Vth and ON-Resistance Control
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Solution Overview
Problem
The existing methods for manufacturing high-electron-mobility transistors, such as atomic layer etching, are costly, time-consuming, and can result in surface damage to the barrier layer, leading to increased ON-resistance and reduced product yield due to over-etching and insufficient threshold voltage.
Innovation Solution
A method involving the formation of a protective layer on the semiconductor substrate, followed by an overlay layer, which allows for easier etching and protects the barrier layer, enabling the p-type layer to be patterned before the source and drain are formed, thus controlling threshold voltage and ON-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If atomic layer etching is used to remove the p-type layer, then the transistor can be manufactured with proper threshold voltage, but the manufacturing cost increases and the process time is extended
Solution Approach 1:
The patent segments the gate region into multiple layers: a protective layer covering the gate opening area, an overlay layer surrounding the protective layer, and a p-type layer formed between them. This segmentation allows different etching processes to be applied to different regions, enabling the use of simpler etching methods while maintaining proper threshold voltage control.
Solution Approach 2:
The protective layer is formed in advance before the p-type layer is deposited. This preliminary action protects the underlying semiconductor structure during subsequent etching and processing steps, eliminating the need for complex atomic layer etching to preserve the barrier layer while still achieving proper threshold voltage control.
2Reliability
If atomic layer etching is used to remove the p-type layer, then the threshold voltage can be controlled, but the process becomes more complex and costly
Solution Approach 1:
The gate region is divided into distinct functional zones: a protective layer covering the gate opening, an overlay layer surrounding it, and a p-type layer formed between them. This segmentation simplifies the overall process by allowing standard etching techniques to be used instead of complex atomic layer etching, while still achieving precise threshold voltage control through the structured arrangement of layers.
Solution Approach 2:
The protective layer acts as an intermediary structure that simplifies the manufacturing process. It protects the underlying semiconductor during etching operations, eliminating the need for complex atomic layer etching processes while maintaining proper threshold voltage control through its strategic positioning and material properties.
3Reliability
If the barrier layer is made thinner to increase threshold voltage, then the threshold voltage increases, but the ON-resistance increases due to reduced electric charges
Solution Approach 1:
The patent applies local quality by forming a p-type layer specifically in the gate region between the protective and overlay layers. This localized doping creates a depletion region that enhances threshold voltage control precisely where needed, while the overlay layer extends toward the source and drain to maintain adequate charge density and low ON-resistance in the conduction paths.
Solution Approach 2:
The patent changes the physical and chemical parameters of the semiconductor structure by introducing a p-type layer with specific doping concentrations and thicknesses. This allows independent optimization of threshold voltage (through the p-type layer in the gate region) and ON-resistance (through the overlay layer extending toward source and drain), decoupling these two previously conflicting parameters.
Data Source
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AI summary
A method for manufacturing a high-electron-mobility transistor includes the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes a channel layer and a barrier layer on the channel layer; forming a protective layer on the semiconductor substrate at a position corresponding to a gate opening; forming an overlay layer on the semiconductor substrate in an area around the protective layer, and removing the protective layer to form the gate opening; and forming a p-type layer in and at the gate opening and on the overlay layer. Compared with the prior art, the method for manufacturing a high-electron-mobility transistor lowers the technical threshold of manufacture, allows the threshold voltage (Vth) and ON-resistance (Rds(ON)) of each such transistor to be individually controlled at the desired levels, and can improve product yield effectively.