HEMT Isolation Structure Using Ion Implantation to Cut Leakage

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Solution Overview

Problem

Existing high electron mobility transistors (HEMTs) face challenges in minimizing leakage current, which affects their performance and efficiency, particularly in device isolation regions.

Innovation Solution

The semiconductor device employs an ion implantation process to create a high damage concentration region in the stacked epitaxial layers, acting as a device isolation region that restricts or traps free electrons, thereby inhibiting leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If conventional device isolation methods are used in HEMTs, then manufacturing complexity increases, but leakage current reduction is insufficient

Engineering Contradiction:
Improveleakage currentVSAvoidmanufacturing process complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent changes the physical state and distribution of damage concentration in the semiconductor layer by controlling ion implantation parameters (energy, dose, angle) to create a high damage concentration region that effectively blocks leakage current while maintaining a simplified single-step manufacturing process

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces complex multi-step mechanical isolation structures (trenches, epitaxial growth) with a single ion implantation process that creates electrical isolation through lattice damage, thereby reducing manufacturing complexity while achieving leakage current suppression

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Object-generated harmful factors

If ion implantation is used to create device isolation region, then leakage current is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improveleakage currentVSAvoidion implantation precision
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating a high damage concentration region with specific spatial distribution through ion implantation, where the damage concentration is highest near the heterojunction and decreases with depth, providing targeted leakage current blocking without requiring uniform high precision throughout the entire structure

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses partial action by implanting ions only in specific regions where leakage current occurs (device isolation regions) rather than uniformly across the entire wafer, and by controlling the implantation depth to affect only the necessary portions of the semiconductor layer, thereby reducing overall precision requirements

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces leakage current by creating a high damage concentration region that provides electrical isolation, while also simplifying the manufacturing process.

Implementation Method 1

The ion implantation process implants ions into the stacked epitaxial layers of the semiconductor device to damage the lattice structures of the stacked epitaxial layers

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS12266723B2Semiconductor device and method for forming the same
Publication Date: 2025.04.01 UNITED MICROELECTRONICS CORP
  • US12266723B2 patent drawing
  • US12266723B2 patent drawing
  • US12266723B2 patent drawing

AI summary

A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.