HEMT Negative Capacitor Gate for Power and Frequency
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Solution Overview
Problem
High electron mobility transistors (HEMTs) face limitations in achieving high power and high frequency performance due to constraints on cap layer thickness, which affects carrier density and gate capacitance, leading to reduced output power and cut-off frequencies.
Innovation Solution
Incorporating a ferroelectric oxide (FEO) layer between metal layers in the gate structure of HEMTs, forming a series of positive and negative capacitors, allows for increased cap layer thickness without reducing gate capacitance, thereby enhancing carrier density and output power while maintaining cut-off frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the cap layer thickness is increased to enhance carrier density and output power, then the gate capacitance is reduced, leading to lower cut-off frequencies
Solution Approach 1:
A ferroelectric oxide (FEO) layer is introduced as an intermediary component between the gate metal layers, forming a negative capacitor that mediates the relationship between gate capacitance and cap layer thickness. The FEO layer's negative capacitance compensates for the capacitance reduction caused by thicker cap layers, enabling both high output power and high cut-off frequency performance
Solution Approach 2:
The patent changes the electrical parameter of the gate structure by incorporating a ferroelectric material with negative capacitance characteristics. This parameter change allows the system to achieve higher carrier density through increased cap layer thickness while maintaining or enhancing gate capacitance through the negative capacitance effect of the FEO layer
2Productivity
If the cap layer thickness is increased to increase carrier density, then transconductance is improved, but gate capacitance is reduced
Solution Approach 1:
The ferroelectric oxide layer acts as an intermediary that decouples the relationship between cap layer thickness and gate capacitance. By introducing this intermediate layer with negative capacitance, the system can achieve higher carrier density and transconductance without suffering from capacitance reduction
Solution Approach 2:
The gate structure is transformed into a composite material system combining conventional metals with ferroelectric oxide. This composite structure exhibits emergent properties where the negative capacitance of the FEO layer combines with the positive capacitance of the cap layer to achieve enhanced overall gate capacitance despite increased cap layer thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables higher transconductance and output power for HEMTs by stabilizing negative capacitance, allowing thicker cap layers that would otherwise reduce gate capacitance, thus improving performance for high-power and high-frequency applications.
Implementation Method 1
Incorporating a ferroelectric oxide (FEO) layer between metal layers in the gate structure of HEMTs, forming a series of positive and negative capacitors
Implementation Method 2
Incorporating a ferroelectric oxide (FEO) layer between metal layers in the gate structure of HEMTs, forming a series of positive and negative capacitors, allows for increased cap layer thickness without reducing gate capacitance
Implementation Method 3
a semiconductor structure including a channel layer and a cap layer arranged on the channel layer to form a two dimensional electron gas (2-DEG) channel at an interface of the channel layer and the cap layer
Implementation Method 4
a gate arranged on the cap layer between the source and the drains, such that the conductivity of the 2-DEG channel can be modulated in response to applying voltage to the gate
Data Source
AI summary
A high electron mobility transistor includes a semiconductor structure having a channel layer and a cap layer forming a two dimensional electron gas (2-DEG) channel, and a source, a drain, and a gate electrodes. The gate is arranged on the cap layer between the source and the drains, such that the conductivity of the 2-DEG channel is modulated in response to applying voltage to the gate. The cap layer includes III-N material. The gate has a layered structure including a bottom metal layer arranged on cap layer, a ferroelectric oxide (FEO) layer arranged on bottom metal layer, and a top metal layer arranged on the FEO layer. Thickness of FEO layer is less than t.sub.cap/(2.alpha..epsilon..sub.cap), wherein .alpha. is a parameter of material of FEO layer, t.sub.cap is thickness of cap layer, and .epsilon..sub.cap is electric permittivity of cap layer.