HEMT Passivation Layer Etch Stop Structure

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Solution Overview

Problem

The performance of High-electron-mobility transistors (HEMTs) is compromised due to the deterioration of the passivation layer during manufacturing, leading to high interfacial density of states, interfacial traps, degraded drain current, and increased off-current leakage, as the surface of the compound layer is exposed and affected by the deposition and etching processes.

Innovation Solution

A semiconductor structure is proposed with a composite passivation layer system comprising a first and second passivation layer, along with an etch stop layer, to protect the compound layer surface during HEMT manufacturing, ensuring the surface integrity is maintained and electrical performance is enhanced.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the passivation layer is etched away to form gate recess, then the gate terminal can be formed, but the compound layer surface becomes exposed and deteriorated, causing degraded drain current and increased off-current leakage

Engineering Contradiction:
Improvegate terminal formationVSAvoidelectrical performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent deposits a second passivation layer over the first passivation layer before performing the gate recess etching process. This second passivation layer serves as a protective barrier during etching, preventing etchant from reaching and damaging the compound layer surface. After etching is complete, the second passivation layer is removed, revealing a clean, undamaged compound layer surface that maintains excellent electrical performance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The second passivation layer acts as an intermediary protective layer between the etching process and the compound layer. It temporarily absorbs the harmful effects of the etchant, allowing the gate recess to be formed while shielding the underlying compound layer from damage. This intermediary layer is then removed after serving its protective purpose.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple deposition and etching processes are performed, then the HEMT structure is completed, but the accumulated damage to the passivation layer and compound layer interface increases, leading to threshold voltage fluctuation and performance degradation

Engineering Contradiction:
ImproveHEMT manufacturing completionVSAvoidinterface quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the manufacturing process into distinct stages, each with its own dedicated passivation layer protection. The first passivation layer protects during metal deposition, the second passivation layer protects during gate recess etching, and the third passivation layer provides final protection. This segmentation ensures that each sensitive interface is protected during its specific vulnerable process while allowing other processes to proceed without restriction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary protection strategies for each known damaging process in the manufacturing sequence. Before metal deposition, a first passivation layer is deposited to prevent metal contamination. Before gate recess etching, a second passivation layer is deposited to prevent etch damage. Before final processing, a third passivation layer is deposited. This systematic preliminary protection approach ensures that each interface maintains high quality throughout the multi-step manufacturing process.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents surface damage, improving the electrical performance of HEMTs by maintaining the integrity of the compound layer surface, reducing interfacial traps, and stabilizing drain current and threshold voltage fluctuations.

Implementation Method 1

a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer

Methodology Applied
Scientific EffectPhysical barrier protection:

Implementation Method 2

an etch stop layer disposed between the lower portion and the upper portion of the passivation layer

Methodology Applied
Scientific EffectEtch selectivity:

Data Source

PatentUS10269948B2High-electron-mobility transistor (HEMT) structure capable of protecting a III-V compound layer and manufacturing method thereof
Publication Date: 2019.04.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10269948B2 patent drawing
  • US10269948B2 patent drawing
  • US10269948B2 patent drawing

AI summary

A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.