HEMT Structure with Segmented Barrier Layers for High Pinch-Off Voltage
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Solution Overview
Problem
Current high electron mobility transistors (HEMTs) face challenges in achieving a pinch-off voltage greater than 1 volt and high maximum current density, particularly in enhancement mode switch devices, which are essential for various applications including power-switching and RF amplification.
Innovation Solution
The HEMT structure incorporates a substrate with epitaxially deposited layers, including a buffer layer, channel layer, spacer layer, and barrier layer, optimized in composition and thickness to create a heterojunction that enables a two-dimensional electron gas formation, along with a T-shaped gate structure and ohmic contacts, to achieve a pinch-off voltage greater than 1 volt and high current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional HEMT structures are used, then device fabrication is simplified, but pinch-off voltage cannot exceed 1 volt and maximum current density is limited
Solution Approach 1:
The device is segmented into multiple functional layers with distinct purposes: a buffer layer for substrate preparation, a channel layer for charge transport, and a barrier layer for electron confinement. This segmentation allows each layer to be independently optimized for its specific function, enabling the achievement of high pinch-off voltage through precise control of the barrier layer properties without compromising overall device performance
Solution Approach 2:
Different regions of the device structure are given different material compositions and doping concentrations tailored to local requirements. The barrier layer uses specific aluminum composition ratios to create the necessary potential well, while the channel layer maintains high mobility through controlled doping. This local quality differentiation enables simultaneous achievement of high pinch-off voltage and high current density
2Reliability
If heterojunction layers are optimized for high pinch-off voltage, then enhancement mode switching is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The buffer layer is deposited first to prepare the substrate surface and establish the crystal orientation before the critical channel and barrier layers are formed. This preliminary action creates a stable foundation that reduces sensitivity to subsequent layer thickness variations, enabling enhancement mode switching to be achieved with more relaxed manufacturing tolerances
Solution Approach 2:
The invention utilizes changes in material composition parameters, specifically the aluminum composition ratio in the barrier layer and doping concentrations in the channel layer, to tune the device characteristics. By adjusting these parameters within optimized ranges, enhancement mode switching is achieved while maintaining manufacturing feasibility through standard epitaxial growth processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for an enhancement mode switch device with a pinch-off voltage greater than 1 volt and a maximum current density of about 2.5 amperes per millimeter of gate width, enhancing reliability and performance in power-switching and RF amplification applications.
Implementation Method 1
a heterojunction is generally formed between two semiconductor materials having different bandgaps
Implementation Method 2
optimized in composition and thickness to create a heterojunction that enables a two-dimensional electron gas formation
Data Source
AI summary
Embodiments of the present disclosure describe structural configurations of an integrated circuit (IC) device such as a high electron mobility transistor (HEMT) switch device and method of fabrication. The IC device includes a buffer layer formed on a substrate, a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, a spacer layer formed on the channel layer, a barrier layer formed on the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga), a gate dielectric directly coupled with the spacer layer or the channel layer, and a gate formed on the gate dielectric, the gate being directly coupled with the gate dielectric. Other embodiments may also be described and/or claimed.