Self-Aligned Gate Electrode for HEMT Gap Elimination
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Solution Overview
Problem
Conventional methods of gate electrode formation in High Electron Mobility Transistors (HEMTs) lead to gaps between the gate electrode and the semiconductor surface, causing current collapse and increased capacitance, which negatively impact device performance.
Innovation Solution
A method of forming a gate electrode with portions extending on both the protective layer and a dielectric layer, where the gate electrode is self-aligned to the protective layer, reducing gaps and capacitance by using a stair-step profile and a high-quality oxide layer with a lower dielectric index than the protective layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods of gate electrode formation are used, then the gate electrode can be formed in the etched portion of the dielectric, but gaps are formed between the edges of the dielectric and the gate electrode, causing current collapse and drift
Solution Approach 1:
The patent applies preliminary action by forming the gate electrode to extend beyond the dielectric edges before final processing steps. The gate electrode is intentionally over-formed to protrude past the dielectric boundaries, ensuring that no gaps exist between the gate electrode and dielectric edges. This preliminary extension prevents the formation of unpassivated semiconductor surfaces that would cause current collapse.
Solution Approach 2:
The patent employs asymmetry by creating a non-uniform gate electrode structure that extends asymmetrically beyond the dielectric edges. The gate electrode has different dimensions relative to the dielectric on opposite sides, with the metal portion deliberately designed to overhang the dielectric boundaries. This asymmetric configuration ensures complete coverage and eliminates gap formation.
2Reliability
If a passivation layer is formed in the gap after gate electrode formation, then the gap can be filled, but the passivation properties are inferior to the pre-gate dielectric
Solution Approach 1:
The patent applies preliminary action by forming the gate electrode structure in advance to extend beyond the dielectric edges, eliminating the need for subsequent gap-filling passivation steps. The gate electrode is deliberately designed to overhang the dielectric boundaries during the formation process, so that no gaps require post-processing passivation. This approach maintains the superior passivation properties of the original dielectric material.
3Manufacturing precision
If the mask and sacrificial layer are removed prior to gate electrode formation, then the gate electrode can completely fill the etched portion and form wings on the dielectric surface, but gate-drain and gate-source capacitance are increased
Solution Approach 1:
The patent applies local quality by creating different regions of the gate electrode with different functions. The gate electrode has a central portion that provides the primary gating function and lateral portions (wings) that extend onto the dielectric surface. By carefully controlling the local dimensions and positioning of these different regions, the patent achieves precise alignment while managing parasitic capacitance effects through the specific geometry of the extended portions.
4Ease of manufacture
If a T-shaped gate electrode is deposited into the etched portion of the dielectric, then the gate structure can be formed, but gaps are formed between the dielectric edges and gate electrode due to isotropy of the dielectric etch
Solution Approach 1:
The patent applies preliminary action by intentionally designing the gate electrode formation process to extend the metal gate material beyond the dielectric edges. Rather than attempting to perfectly match the gate electrode dimensions to the dielectric boundaries, the process deliberately over-forms the gate electrode to ensure it protrudes past all dielectric edges, preemptively eliminating any potential gaps before subsequent processing steps.
Data Source
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AI summary
Transistors are fabricated by forming a protective layer having an opening extending therethrough on a substrate, and forming a gate electrode in the opening. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion. Related devices and fabrication methods are also discussed.