GaN HEMT Source Field Plates Under Gate Runners
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-voltage transistors, such as GaN HEMT devices, face challenges in achieving high performance without increasing size, particularly in reducing gate resistance and parasitic capacitance associated with the field plate, while avoiding additional routings that would enlarge the device.
Innovation Solution
The HEMT device incorporates a field plate extending from the source contact layer, positioned close to the channel region, with openings above the gate metal layer allowing the gate runner layer to connect, thereby reducing resistance and parasitic capacitance without increasing the device size, and achieving significant size efficiency through vertical overlap of metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a field plate is added above the gate structure to improve switching speed, then the switching speed is improved, but the parasitic capacitance increases and the device size increases
Solution Approach 1:
The field plate is repositioned from a horizontal placement above the gate structure to a vertical placement beneath the gate runner layer and above the gate metal layer. This dimensional change allows the field plate to maintain its switching speed enhancement function while reducing parasitic capacitance by being closer to the channel region, and eliminates the need for additional horizontal routing space.
Solution Approach 2:
The field plate is nested within the vertical stack of the gate structure, positioned between the gate runner layer and the gate metal layer. This nesting approach integrates the field plate into the existing gate structure without requiring additional horizontal space, thereby improving switching speed without increasing device size.
2Reliability
If the gate structure is designed to reduce resistance, then the gate resistance is reduced, but the device size increases due to additional routings
Solution Approach 1:
The gate runner layer is positioned vertically above the field plate, creating a multi-layer vertical structure. This vertical stacking reduces the horizontal routing length required for gate connections, thereby reducing gate resistance without increasing the device footprint.
3Object-generated harmful factors
If the field plate is positioned closer to the channel region, then the parasitic capacitance is reduced, but the gate structure becomes more complex
Solution Approach 1:
The field plate structure is merged with the gate structure by positioning it vertically between the gate runner layer and the gate metal layer. This integration allows the field plate to be positioned close to the channel region for reduced parasitic capacitance while sharing the same vertical space as the gate structure, thereby avoiding additional structural complexity.
Data Source
AI summary
A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.