Asymmetric HEMT Spacer Layout for 2DEG and Depletion Control

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Solution Overview

Problem

Current semiconductor device structures, particularly in HEMT devices, face challenges in controlling the depletion layer and two-dimensional electron gas (2DEG) concentration due to limitations in spacer length and dopant distribution, which affect device performance, especially at low and high voltage applications and radio frequency operations.

Innovation Solution

A semiconductor device structure is designed with asymmetrical spacers, where the first spacer has a specific dopant concentration gradient and length, and the second spacer has a longer length, allowing for controlled etching and formation of an asymmetrical nitride semiconductor layer, enabling precise control of the depletion layer and 2DEG concentration without the need for lithography techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If symmetrical spacers of equal length are used, then the manufacturing process is simple, but the depletion layer and 2DEG concentration cannot be precisely controlled

Engineering Contradiction:
Improvecontrol of depletion layer and 2DEG concentrationVSAvoidspacer structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by forming first and second spacers with different lengths on opposite sides of the gate structure. The first spacer has a first length and the second spacer has a second length that is greater than the first length, creating an asymmetric configuration that enables precise control of the depletion layer and 2DEG concentration while maintaining manufacturing simplicity through self-aligned formation processes.

Inventive Principle:
Principle #4Asymmetry

2Manufacturing precision

If lithography techniques are used to control spacer dimensions, then manufacturing precision is improved, but device complexity and process steps increase

Engineering Contradiction:
Improvespacer length controlVSAvoidnumber of process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent employs self-service by forming the first and second spacers through a self-aligned process where the spacers are grown or deposited directly adjacent to the gate structure without requiring separate lithography steps for patterning. The asymmetric lengths are achieved through selective etching or deposition processes that use the gate structure itself as a reference, eliminating the need for additional lithography techniques to control spacer dimensions.

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If uniform dopant distribution is used in spacers, then the manufacturing process is simple, but the 2DEG concentration control is insufficient

Engineering Contradiction:
Improve2DEG concentration controlVSAvoiddopant distribution process
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies local quality by introducing dopants with different concentrations into the first and second spacers. The dopant concentration in the first spacer differs from the dopant concentration in the second spacer, creating localized variations in electrical properties that enable precise control of the 2DEG concentration and depletion layer characteristics while maintaining ease of manufacture through selective doping processes.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240371969A1Semiconductor device structures and methods of manufacturing the same
Publication Date: 2024.11.07 INNOSCIENCE (SUZHOU) TECH CO LTD
  • US20240371969A1 patent drawing
  • US20240371969A1 patent drawing
  • US20240371969A1 patent drawing

AI summary

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure, a first spacer, a second spacer and a drain electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The first spacer is disposed adjacent to a first surface of the gate structure. The second spacer is disposed adjacent to a second surface of the gate structure. The drain electrode is disposed relatively adjacent to the second spacer than the first space. The first spacer has a first length, and the second spacer has a second length greater than the first length along the first direction.