Enhancement Mode III-Nitride HEMT Passivation for Drain Lag Reduction
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Solution Overview
Problem
The manufacturing of enhancement mode III-nitride HEMTs faces challenges due to the difficulty in selectively etching the p-GaN layer from the AlGaN barrier, leading to exposed surfaces between the gate and drain that are not passivated, resulting in drain lag and poor device performance.
Innovation Solution
A method involving the use of a high-temperature silicon nitride passivation layer formed over III-nitride layers, with a recessed gate region created by selectively removing the passivation layer only in the gate area, allowing for partial filling with a p-GaN layer and maintaining protection through the passivation layer for source/drain contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the p-GaN layer is selectively etched from the AlGaN barrier to enable enhancement mode operation, then the device can achieve enhancement mode characteristics, but the surface between gate and drain becomes exposed and unpassivated, resulting in drain lag
Solution Approach 1:
The passivation layer is deposited over the entire surface before any etching operations. This preliminary passivation prevents the formation of unpassivated surfaces that would otherwise occur after selective etching of the p-GaN layer, thereby eliminating drain lag while maintaining enhancement mode operation capability
Solution Approach 2:
Instead of the conventional approach of etching the p-GaN layer first and then attempting to passivate the exposed surface, the invention inverts the sequence by depositing the passivation layer first and then etching through it in the gate region. This ensures the surface remains passivated throughout the process, preventing drain lag
2Ease of manufacture
If the passivation layer is completely removed in the gate region to form a recessed gate, then proper gate contact can be formed, but the source/drain contacts require additional etching through the passivation layer
Solution Approach 1:
The passivation layer removal is segmented into two distinct regions: complete removal in the gate region to form the recessed gate, and partial removal or opening in the source/drain regions. This segmentation allows each contact type to be optimized independently while maintaining the overall passivation structure
Solution Approach 2:
Different treatments are applied to different regions of the passivation layer: in the gate region it is completely removed to expose the underlying layer for gate contact formation, while in the source/drain regions selective openings are created. This local differentiation optimizes each region for its specific function while maintaining overall device integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach preserves the passivation layer, reducing drain lag and improving device performance by protecting the surface and maintaining the integrity of the III-nitride device, resulting in better dispersion behavior and reduced sensitivity to high-temperature dielectric deposition.
Implementation Method 1
a passivation layer (301) comprising high temperature (HT) silicon nitride overlying and in contact with an upper layer (203, 204—not shown) of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD
Implementation Method 2
forming a recessed gate region by removing substantially completely the passivation layer (301) selectively towards the underlying upper layer (203, 204—not shown) only in the gate region
Data Source
AI summary
Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts.