Hermetic Seal for 3D Chip Stacking via Perimeter Bonding
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Solution Overview
Problem
Current multi-chip module (MCM) technology faces challenges with mechanical stability, corrosion, and contamination in 3D wafer-to-wafer vertical stack integration, particularly at the edges of bonded patterns, leading to bonding failures and reduced reliability.
Innovation Solution
A sealed microelectronic structure is created by applying a continuous length of bonding material around the perimeter of each chip or wafer, with support columns extending outward to mate and form a seal when chips or wafers are overlapped and heated, providing mechanical stress endurance and protection against environmental damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MCM technology is used to stack multiple chips on a common substrate, then packaging density and system speed are improved, but mechanical stability and reliability deteriorate due to bonding failures at the edges of bonded patterns
Solution Approach 1:
The patent applies preliminary action by forming a continuous bonding material perimeter around the edges of chips/wafers before the actual chip stacking process. This pre-established bonding perimeter ensures that when chips are stacked and bonded, the edge regions are already prepared with proper bonding material distribution, preventing bonding failures during the subsequent stacking and bonding operations.
Solution Approach 2:
The patent applies local quality by providing different bonding material configurations in different regions of the chip/wafer. Specifically, a continuous bonding material perimeter is provided at the edges where bonding failures commonly occur, while the central regions can have different bonding characteristics. This localized approach addresses the specific problem at bond edges without affecting the entire chip structure.
2Volume of moving object
If chips are stacked in 3D vertical configuration, then system size and weight are reduced, but mechanical stress and susceptibility to damage increase
Solution Approach 1:
The patent applies composite materials by combining the chip/wafer substrate with a continuous bonding material perimeter that has different mechanical properties. This composite structure provides both the electrical functionality of the chip and the enhanced mechanical strength of the bonding material perimeter, which acts as a reinforcement layer that distributes and absorbs mechanical stresses in the 3D stacked configuration.
Solution Approach 2:
The patent applies beforehand cushioning by providing a continuous bonding material perimeter that acts as a protective cushion before mechanical damage can occur. This bonding material perimeter absorbs and distributes mechanical stresses, preventing crack propagation and protecting the chip edges from chipping and other mechanical damage during handling and operation of the 3D stacked structure.
3Reliability
If bonding material is applied at the edges of chips, then hermetic seal and mechanical protection are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies flexible shells and thin films by using a continuous bonding material perimeter that can conform to the chip/wafer edges and provide hermetic sealing. This bonding material perimeter acts as a flexible seal that accommodates slight variations in chip dimensions and surface irregularities, creating an effective hermetic seal without requiring complex rigid sealing structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances mechanical stability, prevents corrosion and contamination, and improves bonding yield by creating a hermetic seal that maintains the integrity of electrical components, while allowing for full-wafer processing and thermal dissipation.
Implementation Method 1
A seal between the at least two chips is formed when the at least two chips are mated together such that the bonding material on each chip is in mating relation to one another. The bonding material is heated to form the seal.
Data Source
AI summary
A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.