Hermetic Via Trenches With Partial Dielectric Fill for Low Capacitance
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Solution Overview
Problem
Existing semiconductor components with vias suffer from high parasitic capacitances, which can cause leakage currents, damage, and disrupt high-frequency operations, and there is a need for a method to reduce these capacitances while ensuring hermetic sealing and cost-effectiveness for mass production.
Innovation Solution
The method involves forming vertical trenches around the via region, partially filling them with a dielectric to reduce parasitic capacitances, and hermetically sealing them to protect the via region from the atmosphere, while maintaining electrical insulation and mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical trenches around via region are completely filled with dielectric, then electrical insulation is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies partial filling of vertical trenches with dielectric material instead of complete filling. The dielectric is deposited to cover the via region and surrounding structures, but the trenches are intentionally left partially empty, creating air gaps that reduce parasitic capacitance while maintaining sufficient electrical insulation through the deposited dielectric layers
2Reliability
If vertical trenches are hermetically sealed with dielectric, then protection from atmosphere is improved, but mechanical stress increases
Solution Approach 1:
The patent uses composite material structures combining deposited dielectric layers with remaining air spaces in the vertical trenches. This composite structure provides hermetic sealing through the dielectric coating while the air gaps reduce mechanical stress on the via region and surrounding structures
3Ease of manufacture
If via region is exposed to atmosphere, then manufacturing simplicity is maintained, but leakage currents and damage occur
Solution Approach 1:
The patent applies preliminary protective action by depositing dielectric material over the via region and surrounding structures before final processing steps. This creates a protective barrier that prevents leakage currents and damage from atmospheric exposure while maintaining manufacturing simplicity through integration with existing deposition processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces parasitic capacitances to femtofarad levels, ensures hermetic sealing, and maintains low mechanical stress, making it suitable for flexible and reliable semiconductor components with reduced electrical interference.
Implementation Method 1
parasitic capacitances that occur are considerably reduced
Implementation Method 2
The vertical trenches are only partially filled with a dielectric
Implementation Method 3
hermetically sealing and cost-effectiveness for mass production
Data Source
AI summary
In a first aspect, the invention relates to a method for producing a via for a semiconductor component. The semiconductor component comprises a via region which is enclosed by vertical trenches. The vertical trenches are only partially filled with a dielectric, so that in particular the parasitic capacitances that occur have been considerably reduced.In a second aspect, the invention relates to a semiconductor component produced by the method according to the invention.