Hermetic Wafer Level Packaging via Titanium Alloy Diffusion Bonding
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Solution Overview
Problem
Existing wafer level packaging techniques are expensive and not fully compatible with current CMOS fabrication processes, limiting their effectiveness in accommodating smaller semiconductor device sizes and increasing complexity in processing and manufacturing.
Innovation Solution
A method involving the use of titanium alloy bonding pads and metal diffusion for bonding semiconductor wafers, which allows for lower bonding temperatures, reduced bonding area, and compatibility with CMOS processes, enabling efficient and hermetic packaging of MEMS devices without melting, thus avoiding material shifting and defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing wafer level packaging techniques are used, then packaging can be achieved, but the process is expensive and not fully compatible with current CMOS fabrication processes
Solution Approach 1:
The patent changes the bonding parameters by using titanium alloy bonding pads with specific material properties that enable bonding at lower temperatures and with different thermal characteristics, making the process compatible with CMOS fabrication while reducing manufacturing complexity
Solution Approach 2:
The patent employs composite material structures including titanium alloy bonding pads combined with specific underlayer and overlay materials, creating a multi-layer composite structure that achieves both CMOS compatibility and cost-effective manufacturing
2Strength
If traditional bonding methods are used, then bonding strength can be achieved, but thermal stress increases and material shifting occurs
Solution Approach 1:
The patent reduces thermal stress by changing the bonding temperature parameter to lower values and by selecting titanium alloy materials with favorable thermal expansion properties, thereby maintaining bonding strength while minimizing thermal stress and preventing material shifting
3Strength
If higher bonding temperatures are used, then bonding strength improves, but thermal stress increases and defects occur
Solution Approach 1:
The patent optimizes the bonding temperature parameter to a lower range that is sufficient for achieving strong bonds with titanium alloy pads, thereby preventing material shifting and defects while maintaining adequate bonding strength
Solution Approach 2:
The patent uses titanium alloy bonding pads that are specifically designed for the bonding process, sacrificing the bonding pad material to achieve the bond while protecting the underlying device structures from thermal damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermal stress, provides high bonding strength, lowers resistivity, and is cost-effective by utilizing existing CMOS-compatible materials, ensuring efficient and reliable wafer level packaging compatible with current semiconductor technologies.
Implementation Method 1
bonding the first and second wafers together through the first and second bonding pads
Data Source
AI summary
Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.