Hetero Junction Semiconductor Gate Electrode Positioning
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Solution Overview
Problem
Conventional semiconductor devices with hetero junctions face challenges in minimizing on-resistance due to suboptimal gate and drain field distributions, leading to higher resistance and inefficiencies in current flow.
Innovation Solution
The semiconductor device incorporates a hetero semiconductor region with an acute angle at the junction end part, allowing for a shorter distance between the gate electrode and the junction end part, which enhances the gate and drain fields, thereby reducing on-resistance. This is achieved through precise etching and masking techniques to form a gate insulating film and gate electrode configuration that applies higher fields to the triple point, thinning the energy barrier and improving conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode is positioned away from the junction end part by a conventional distance, then the device structure is simpler and easier to manufacture, but the on-resistance increases due to suboptimal gate and drain field distributions
Solution Approach 1:
The patent applies parameter changes by precisely controlling the positional parameters of the gate electrode relative to the junction end part. Specifically, the gate electrode is positioned such that the distance from the junction end part to the contact point is smaller than the gate insulating film thickness, and the shortest distance from the shortest point of the gate electrode to the junction end part defines a specific geometric relationship. This parameter optimization enhances gate and drain field distributions, thereby reducing on-resistance while maintaining manufacturability through defined geometric constraints.
2Reliability
If the distance between the gate electrode and junction end part is reduced, then the gate and drain fields are enhanced improving conductivity, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating a non-uniform spatial distribution of electric fields through the optimized gate electrode positioning. The configuration ensures that the region near the junction end part experiences enhanced gate and drain fields due to the reduced distance, while other regions maintain conventional field distributions. This localized field enhancement improves conductivity at the critical junction area without requiring uniform changes throughout the entire device structure.
Solution Approach 2:
The patent utilizes dimensional analysis by defining the gate electrode position through multiple geometric constraints: the distance from the junction end part to the contact point relative to the gate insulating film thickness, and the shortest distance from the shortest point of the gate electrode to the junction end part. This multi-dimensional geometric specification provides a comprehensive framework that guides manufacturing processes while ensuring the desired field enhancement effect.
Data Source
AI summary
A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.