Hetero-Mesh Interconnect With Split Merge Switches
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Solution Overview
Problem
Traditional interconnect architectures, such as ring architectures, face challenges in scaling to support growing numbers of cores in multi-core processors, leading to increased latency and limited bandwidth, especially when dealing with structurally dissimilar processing elements and varying bandwidth demands.
Innovation Solution
The introduction of a hetero-mesh architecture that supports structurally heterogeneous tiles with varying wire densities and potentially different clock frequencies, using Split Merge Switches (SMS) to seamlessly connect parts of the mesh, allowing for a monolithic protocol layer and efficient bandwidth management across diverse processing elements and memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional ring interconnect architectures are used, then device complexity is reduced, but bandwidth and latency characteristics deteriorate when scaling to support growing numbers of cores
Solution Approach 1:
The patent segments the monolithic mesh interconnect into multiple sub-meshes, each with its own clock domain and wire density. This segmentation allows each sub-mesh to be optimized independently for its specific bandwidth and latency requirements while maintaining overall system functionality. The mesh is divided into regions that can operate autonomously, reducing the complexity burden on any single region while improving overall performance.
Solution Approach 2:
Different regions of the mesh interconnect are assigned different wire densities and clock frequencies based on their specific performance requirements. High-bandwidth regions use denser wiring and higher clock frequencies, while lower-demand regions use sparser wiring and lower frequencies. This local optimization allows the system to achieve high productivity in critical areas without compromising the entire system for maximum performance.
2Productivity
If wire density is increased to support high bandwidth requirements, then bandwidth is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements different wire densities in different regions of the mesh interconnect based on local bandwidth requirements. Regions requiring high bandwidth have denser wire arrangements, while regions with lower bandwidth demands have sparser wiring. This localized approach allows high bandwidth performance where needed without subjecting the entire interconnect to high manufacturing complexity.
Solution Approach 2:
The mesh interconnect is segmented into multiple sub-meshes with different wire density characteristics. Each sub-mesh can be manufactured independently with optimized wire density for its specific requirements, reducing the overall manufacturing complexity compared to a uniformly dense interconnect while maintaining high bandwidth capability in critical regions.
3Device complexity
If a monolithic protocol layer is used, then device complexity is reduced, but adaptability to structurally heterogeneous tiles deteriorates
Solution Approach 1:
The patent implements different clock frequencies and wire densities in different regions of the mesh while maintaining a single monolithic protocol layer. This allows structurally heterogeneous tiles with varying bandwidth and latency requirements to coexist within the same protocol framework. Each region can be optimized for its specific tile characteristics without requiring separate protocol layers, thus maintaining simplicity while achieving adaptability.
Solution Approach 2:
The mesh interconnect incorporates dynamic clock frequency adjustment capabilities that allow different regions to operate at different frequencies based on their specific workload and structural requirements. This dynamic adaptation enables the system to accommodate heterogeneous tiles with varying performance characteristics while maintaining a unified protocol layer, as the protocol can adapt to frequency changes without requiring structural modifications.
Data Source
AI summary
A hetero-mesh architecture is provided to enable varying densities of tile in a multi-core processor. The hetero-mesh architecture includes areas with different tile sizes and wire densities operating and different bandwidths. A split merge switch is utilized between the different parts of the hetero-mesh to enable the sending of packets from tiles in one area of the hetero-mesh to another area of the hetero-mesh while employing a single end to end communication protocol.