Heterogeneous Thread Scheduling Power-Performance Balance

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Solution Overview

Problem

Mobile computing devices face challenges in balancing power management and performance, leading to user dissatisfaction due to inefficient battery life and thermal issues, as existing power management strategies often compromise device performance.

Innovation Solution

Heterogeneous thread scheduling techniques are implemented, which distribute processing workloads across heterogeneous processing cores based on periodic power management assessments and thread-specific policies, allowing for intelligent switching between power-efficient and performance-oriented cores to optimize thread placement and resource allocation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If power management strategies control processor utilization, then battery life is extended, but device performance deteriorates

Engineering Contradiction:
Improvebattery lifeVSAvoiddevice performance
Core Design Contradiction:
Duration of action of moving objectVSProductivity

Solution Approach 1:

The processor is segmented into multiple heterogeneous cores with different power and performance characteristics. The system divides the processing workload across these cores based on task requirements, allowing simultaneous operation of power-efficient cores for background tasks and performance-oriented cores for demanding applications, thus resolving the contradiction between battery life and device performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adjusts processor core states and thread placement based on real-time power management assessments and thread-specific policies. This dynamic scheduling allows the system to optimize the balance between power consumption and performance execution by activating or deactivating cores as needed, preventing both battery drain and performance degradation

Inventive Principle:
Principle #15Dynamics

2Productivity

If processor operates at or near capacity, then device functionality is enhanced, but thermal conditions worsen

Engineering Contradiction:
Improvedevice functionalityVSAvoidthermal conditions
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The processor is divided into heterogeneous cores that can be selectively activated. When thermal conditions deteriorate, the system can migrate threads from high-performance cores to power-efficient cores or place performance-oriented cores into low-power states, maintaining device functionality while reducing thermal output through intelligent core selection and workload distribution

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes operational parameters by adjusting core states (active, idle, low-power) and thread placement based on thermal conditions. This allows the processor to maintain enhanced functionality when needed while switching to lower-power configurations when thermal conditions worsen, effectively managing the trade-off between device functionality and temperature

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3198429B1Heterogeneous thread scheduling
Publication Date: 2020.11.11 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP3198429B1 patent drawingFigure 1
  • EP3198429B1 patent drawingFigure 2
  • EP3198429B1 patent drawingFigure 3

AI summary

Heterogeneous thread scheduling techniques are described in which a processing workload is distributed to heterogeneous processing cores of a processing system. The heterogeneous thread scheduling may be implemented based upon a combination of periodic assessments of system-wide power management considerations used to control states of the processing cores and higher frequency thread-by-thread placement decisions that are made in accordance with thread specific policies. In one or more implementations, a system workload context is periodically analyzed for a processing system having heterogeneous cores including power efficient cores and performance oriented cores. Based on the periodic analysis, cores states are set for some of the heterogeneous cores to control activation of the power efficient cores and performance oriented cores for thread scheduling. Then, individual threads are scheduled in dependence upon the core states to allocate the individual threads between active cores of the heterogeneous cores on a per-thread basis.