Heterogeneous Annealing for 3D Interconnects Across CTE Mismatch
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Solution Overview
Problem
The challenge in fabricating three-dimensional integrated circuits (3D ICs) lies in achieving planarity of wafer surfaces for direct bonding, which is costly and can result in reduced yield and increased costs due to the need for vertical stacking and interconnection of ICs with different sizes and materials, and the difficulty in forming reliable 3D electrical interconnections across bond interfaces with varying coefficients of thermal expansion (CTE).
Innovation Solution
A method and device that involves thinning one or both elements to reduce stiffness, allowing for direct bonded 3D interconnections by aligning conductive metal portions below insulating portions and using a third wafer with a comparable CTE to increase stiffness, enabling reliable 3D interconnections across the bond interface upon heating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If direct bonding is used to vertically stack ICs with different sizes and materials, then 3D integration density is improved, but manufacturing complexity increases due to the need for surface planarization
Solution Approach 1:
The patent applies parameter changes by modifying the thermal parameters (heating to elevated temperatures) during the bonding process to achieve direct bonding without requiring extensive surface planarization. The temperature parameter is changed to enable the bonding reaction to proceed at surfaces with greater variability, thereby reducing the complexity of surface preparation while maintaining high 3D integration density.
2Manufacturing precision
If conventional wafer fabrication techniques are used for surface preparation, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the thermal parameter by heating the bonded wafers to elevated temperatures (e.g., 100-400°C) during the bonding process. This temperature parameter change enables direct bonding to proceed effectively even with less precisely prepared surfaces, thereby reducing the need for costly conventional wafer fabrication techniques while maintaining adequate bonding precision.
3Adaptability or versatility
If elements with different coefficients of thermal expansion are directly bonded, then material versatility is improved, but reliability decreases due to bond fractures during heating
Solution Approach 1:
The patent applies parameter changes by carefully controlling the temperature parameter during heating. By gradually increasing the temperature and maintaining it within a controlled range, the patent enables direct bonding of materials with different coefficients of thermal expansion without causing bond fractures. The temperature parameter is adjusted to accommodate the CTE differences while still achieving reliable 3D interconnections.
Solution Approach 2:
The patent employs beforehand cushioning by preparing the bonding surfaces with specific properties (such as metal layers with appropriate thickness and composition) that can accommodate the thermal stress generated during heating. These pre-prepared surface structures act as a cushion or buffer that absorbs the differential expansion forces, preventing bond fractures while allowing the use of materials with different CTE values.
4Reliability
If metal direct bonding is used to form 3D interconnections, then electrical connectivity is improved, but manufacturing precision requirements increase due to alignment sensitivity
Solution Approach 1:
The patent applies parameter changes by utilizing the thermal parameter (heating) to enhance the bonding process. The elevated temperature increases the ductility and deformability of the metal layers, allowing them to self-align and conform to each other during bonding. This temperature parameter change reduces the sensitivity to initial alignment precision while still achieving reliable electrical interconnections, as the thermal energy enables the metal to flow and fill in minor misalignments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates the formation of reliable 3D interconnections at higher temperatures, improving the yield and cost-effectiveness of 3D IC fabrication by accommodating CTE differences and preventing bond fractures, thus enhancing the scalability and density of vertical interconnections.
Implementation Method 1
direct bonding where the direct bonding surface preparation uses conventional wafer fabrication techniques
Implementation Method 2
A compression device and method that will facilitate formation of direct bonded 3D interconnections between two elements when heated
Data Source
AI summary
A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.