Heterogeneous Asynchronous Processor with Token Gating
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Solution Overview
Problem
Existing asynchronous processor architectures face inefficiencies due to reliance on non-standard Muller-C elements for handshaking protocols, leading to increased latency and complexity in chip implementation, which can be mitigated by adopting a heterogeneous processor architecture with token-based resource management.
Innovation Solution
The proposed solution involves a heterogeneous asynchronous processor architecture that utilizes a feedback engine to decode instructions and a scheduler to distribute them between basic and advanced execution units (XUs or ALUs) with varying access restrictions, employing token gating and passing logic to optimize resource access and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If non-standard Muller-C elements are used to realize handshaking protocol between clockless computing circuit logics, then asynchronous processing capability is achieved, but device complexity and latency increase
Solution Approach 1:
The patent uses standard logic elements (such as AND gates, OR gates, and NOT gates) to copy and replicate the handshaking functionality of non-standard Muller-C elements. By using readily available standard cells to implement the same logical function, the design achieves asynchronous processing without requiring specialized components, thereby reducing device complexity and easing chip implementation while maintaining the automation of asynchronous operation
2Productivity
If homogeneous processor architecture is used with uniform resource access, then implementation simplicity is maintained, but processing efficiency and latency increase
Solution Approach 1:
The patent implements a heterogeneous processor architecture where different execution units (EU0, EU1, EU2, etc.) have differentiated resource access permissions. Specifically, certain execution units are granted direct access to specific resources (such as EU0 directly accessing resource A, EU1 directly accessing resource B) while others have restricted access. This local differentiation of access rights allows instructions to be executed by the most appropriate execution unit without unnecessary arbitration delays, thereby improving processing efficiency and reducing latency compared to a homogeneous architecture where all units have uniform access
3Reliability
If token ring regulates access to system resources with sequential token passing, then resource access control is achieved, but processing speed decreases due to access restrictions
Solution Approach 1:
The patent dynamically adapts the token access mechanism by allowing execution units with direct resource access permissions to bypass the sequential token passing protocol for specific resources. When an execution unit has pre-granted access rights to a resource, it can access that resource immediately without waiting for the token to circulate through the entire ring. This dynamic adjustment maintains reliable resource access control for shared resources while significantly improving processing speed for operations that can utilize directly accessible resources
Data Source
AI summary
Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction requires access to the resource. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.