Heterogeneous Processor Cache Coherence via Memory Region Segmentation
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Solution Overview
Problem
Current cache coherence techniques for heterogeneous processors, such as CPUs and GPUs, result in excessive snoop traffic and performance bottlenecks due to differing memory usage rates, and existing solutions require significant changes to application software, making them impractical for widespread adoption.
Innovation Solution
Implementing a memory-region-level monitoring hardware scheme that maintains cache coherence at a finer granularity within processors and a coarser granularity between processors, allowing for reduced snoop traffic and efficient memory management by tracking memory ownership at a region level, thereby optimizing inter-processor communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bus snooping is used to maintain cache coherence between heterogeneous processors, then cache coherence is maintained, but snoop traffic increases excessively causing performance bottlenecks
Solution Approach 1:
The patent segments the shared memory into multiple regions, each region being exclusively allocated to a specific processor. This segmentation eliminates the need for cross-processor snoop traffic for memory accesses within the same region, as each processor can independently access its allocated memory regions without coordinating with other processors. Only inter-region accesses require coherence protocols, significantly reducing overall snoop traffic.
Solution Approach 2:
The patent implements local quality by allowing each processor to have different memory allocation patterns based on its specific needs. The CPU and GPU can have different numbers and sizes of memory regions allocated to them, optimized for their respective workloads. This localized memory management allows each processor to operate efficiently within its own regions without being constrained by uniform coherence protocols across the entire memory space.
2Reliability
If exclusive memory pools are designated at the application level, then cache coherence can be achieved, but application software requires significant changes
Solution Approach 1:
The patent introduces an intermediary layer (the memory management unit or operating system) that automatically manages memory region allocation and tracking. This intermediary handles the complexity of memory region management, translating high-level application memory requests into appropriate region allocations. Applications don't need to be modified because the intermediary automatically enforces the exclusive memory pool semantics, maintaining cache coherence transparently to the application software.
3Reliability
If fine-grained cache coherence is maintained between heterogeneous processors, then cache integrity is preserved, but inter-processor communication bandwidth is consumed excessively
Solution Approach 1:
By segmenting memory into exclusive regions per processor, the patent reduces the scope of coherence monitoring. Instead of monitoring entire memory spaces or large memory blocks, the system only needs to monitor boundaries between regions. This segmentation allows fine-grained coherence tracking only where necessary (at region boundaries), while granting autonomous access within regions, thereby preserving cache integrity where needed while minimizing communication overhead.
Data Source
AI summary
Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity.