Heterogeneous Cache Structure for Low-Voltage Power Efficiency
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Solution Overview
Problem
Current cache structures in integrated circuits face challenges in achieving reliable low-voltage operation while maintaining power efficiency, as reducing voltage leads to increased sensitivity to process variations and transistor mismatches, and larger transistors are undesirable due to area occupancy.
Innovation Solution
A heterogeneous cache structure is introduced, where the cache is divided into portions with varying susceptibility to errors based on operating voltage, allowing for selective deactivation and activation of these portions, thereby reducing cache capacity while minimizing performance penalties through dynamic voltage and frequency scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the voltage is reduced to improve power efficiency, then power consumption is lowered, but reliability deteriorates due to increased sensitivity to process variations and transistor mismatches
Solution Approach 1:
The cache memory is divided into multiple portions (first portion, second portion, third portion) with different transistor size characteristics. Each portion can be independently activated or deactivated based on voltage levels, allowing the system to segment the reliability-risk trade-off across different cache regions.
Solution Approach 2:
Different portions of the cache memory are designed with different transistor sizes to create local quality variations. The first portion has larger transistors for low-voltage reliability, while the second and third portions have progressively smaller transistors, allowing each region to operate optimally at different voltage levels.
2Reliability
If the transistor size is increased to improve reliability at low voltages, then susceptibility to process variations decreases, but cache area increases occupying more than 50 percent of total processor area
Solution Approach 1:
The cache is segmented into portions with different transistor size requirements. Only the first portion uses large transistors when needed for low-voltage operation, while the second and third portions can use smaller transistors, thereby reducing overall cache area compared to a uniform large-transistor design.
Solution Approach 2:
Instead of making all transistors large to ensure reliability across all cache portions, the invention applies large transistors only partially to the first portion when low-voltage operation is required, while allowing smaller transistors in other portions when higher voltages are used.
Data Source
AI summary
A heterogeneous cache structure provides several memory cells into different ways each associated with different minimum voltages below which the memory cells produce substantial state errors. Reduced voltage operation of the cache may be accompanied by deactivating different ways according to the voltage reduction. The differentiation between the memory cells in the ways may be implemented by devoting different amounts of integrated circuit area to each memory cell either by changing the size of the transistors comprising the memory cell or devoting additional transistors to each memory cell in the form of shared error correcting codes or backup memory cells.