Configurable Cache-Way Allocation for Multi-Core Data Coherency
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Solution Overview
Problem
Multi-core systems face coherency issues due to shared memory access, leading to operational inefficiencies and potential outdated data retrieval, especially when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank is implemented, which includes coherent slave interfaces and an external memory master interface, enabling efficient data management through hardware-based coherency and virtual channel establishment to arbitrate memory access requests and ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates due to slow performance and excessive operational time consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency controller that automatically manages cache coherency. The coherency controller includes snoop filter banks, cache tag banks, and memory banks that operate in hardware to detect and resolve coherency issues without software intervention, thereby maintaining reliability while dramatically improving operational efficiency.
Solution Approach 2:
The coherency controller is designed to automatically manage cache coherency without requiring software cache maintenance operations. The hardware-based system self-monitors cache states, detects coherency violations through snoop filters, and resolves conflicts autonomously, eliminating the need for software intervention and improving operational efficiency.
2Adaptability or versatility
If multiple processing cores access shared memory devices, then system functionality is enhanced, but coherency issues arise leading to outdated data retrieval
Solution Approach 1:
The patent introduces a coherency controller as an intermediary between multiple processing cores and shared memory devices. The controller includes snoop filter banks that monitor memory access requests from different cores, cache tag banks that track cached data states, and memory banks that manage shared memory. This intermediary structure enables multiple cores to access shared memory simultaneously while maintaining data coherency through automated conflict detection and resolution.
3Speed
If a core modifies cached data without committing back to shared memory, then access speed is improved, but coherency is compromised causing outdated data for other cores
Solution Approach 1:
The coherency controller implements a feedback mechanism through snoop filter banks that monitor memory access requests from multiple cores. When one core modifies cached data, the controller detects the modification through snoop requests and automatically invalidates or updates corresponding cache entries in other cores. This feedback loop maintains data coherency while allowing cores to benefit from cached data access speed.
Data Source
AI summary
A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.