Heterogeneous Capacitor Structure for High Capacitance Density
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Solution Overview
Problem
Current capacitor designs face challenges in achieving high unit capacitance values while minimizing grain size and parasitic effects, leading to increased circuit board material and costs.
Innovation Solution
A heterogeneous integration capacitor is developed, comprising a semiconductor capacitor, metal-oxide-metal (MoM) capacitor, and metal-insulator-metal (MiM) capacitor connected in parallel, with specific comb-like metal layer structures and oxidation layers to enhance capacitance, reducing grain size and parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a high unit capacitance value is obtained by increasing capacitor size, then capacitance value increases, but grain size becomes large and board material increases
Solution Approach 1:
The capacitor structure is segmented into three distinct capacitor types (MiM, MoM, and semiconductor capacitors) that are integrated together. Each capacitor type contributes to the total capacitance value, allowing the system to achieve high unit capacitance without increasing the overall grain size of a single capacitor component.
Solution Approach 2:
The patent transitions from a single-plane capacitor design to a multi-layer three-dimensional structure. The MiM capacitor uses metal layers separated by insulating layers, the MoM capacitor uses metal-oxide-metal stacks, and the semiconductor capacitor utilizes doped regions in the substrate. This vertical stacking in the third dimension dramatically increases capacitance density without expanding the planar grain size.
2Quantity of substance
If external discrete component capacitance value is increased, then capacitance improves, but volume occupied increases
Solution Approach 1:
The patent embeds multiple capacitor structures within each other in a nested configuration. The semiconductor capacitor is formed within the substrate, the MoM capacitor is built upon it using metal-oxide-metal layers, and the MiM capacitor integrates additional metal-insulator-metal structures. This nested arrangement allows three complete capacitors to occupy the volume of what would traditionally be a single discrete component.
3Ease of manufacture
If traditional capacitor structures are used, then manufacturing is simple, but parasitic effect is large
Solution Approach 1:
The patent merges three different capacitor technologies (MiM, MoM, and semiconductor capacitors) into a single integrated structure that shares common electrodes and interconnection paths. This merging reduces the total number of discrete components and interconnections required, thereby reducing overall parasitic inductance and resistance while maintaining manufacturability through standard semiconductor processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a significant increase in unit capacitance value, improves quality factor, and reduces circuit board material and costs, while effectively integrating capacitors on a semiconductor substrate.
Implementation Method 1
oxidation layers positioned between the first metal layer and the second metal layer and between the second metal layer and the third metal layer
Data Source
AI summary
A heterogeneous integration capacitor and a metal-oxide-metal (MoM) capacitor are provided. The heterogeneous integration capacitor has a first electrode and a second electrode, and includes a substrate, a semiconductor capacitor, the MoM capacitor, and a metal-insulator-metal (MiM) capacitor. These capacitors are sequentially formed on the substrate, and are formed as connected in parallel.