Heterogeneous Chip Emulation Partitioning Debug Modules
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current hardware emulators either have low emulation performance and high turnaround time when using microprocessors, or high emulation performance but long turnaround times when using FPGAs, failing to balance these factors effectively.
Innovation Solution
A method and system that interconnects microprocessors and FPGAs to form a heterogeneous hardware emulation system, where critical design modules requiring frequent debugging are assigned to microprocessors, and mature design modules are assigned to FPGAs, allowing for efficient compilation and co-simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FPGAs are used for hardware emulation, then emulation performance is improved, but compilation time increases and turnaround time becomes long
Solution Approach 1:
The chip design is partitioned into multiple modules that are distributed across both FPGAs and microprocessors. This segmentation allows the system to leverage the high emulation performance of FPGAs for critical modules while using microprocessors for modules requiring frequent debugging, thereby reducing overall compilation time while maintaining high emulation performance.
Solution Approach 2:
The patent combines FPGAs and microprocessors into a heterogeneous hardware emulation system. This merging allows the system to simultaneously exploit the high emulation performance of FPGAs and the fast compilation capabilities of microprocessors, resolving the contradiction between emulation performance and compilation time.
2Loss of time
If microprocessors are used for hardware emulation, then compilation time is reduced and turnaround time is short, but emulation performance deteriorates
Solution Approach 1:
Different quality characteristics are assigned to different parts of the system: FPGAs are used for modules requiring high emulation performance, while microprocessors are used for modules requiring fast turnaround time. This local quality assignment allows each component to operate in its optimal performance regime.
Solution Approach 2:
The system dynamically allocates design modules to either FPGAs or microprocessors based on debugging requirements. Modules requiring frequent debugging are assigned to microprocessors for fast recompilation, while stability-critical modules are assigned to FPGAs for high-performance emulation, making the system adaptable to different operational requirements.
3Device complexity
If homogeneous hardware (only FPGAs or only microprocessors) is used, then system complexity is reduced, but the ability to balance emulation performance and turnaround time is limited
Solution Approach 1:
The heterogeneous hardware emulation system serves multiple functions: it can handle both high-performance emulation requirements and fast-turnaround debugging requirements within the same system. This multi-functionality allows the system to adapt to different verification scenarios without requiring separate homogeneous systems.
Data Source
AI summary
The present invention relates to the field of chip verification technology, and more particularly, to a method and system for emulating a chip design with heterogeneous hardware. It involves the interconnection of microprocessors and FPGAs, where the microprocessors have shorter object code compilation times than the FPGAs' bit files, and the FPGAs have higher emulation performance. The DUT is partitioned into n microprocessors and m FPGAs. The design module D, which requires debugging and correction, is assigned to the microprocessors. Then, the n microprocessors and the m FPGAs are controlled to perform emulation and debugging. Since the compilation time for a microprocessor hosting the design module D is shorter than when using FPGAS, and while ensuring that the mature design modules in the FPGAs have high emulation performance, the method successfully integrates the advantages of the iterative speed of microprocessors and the emulation performance of FPGAs.