Heterogeneous Chip Partitioning With Passive-Memory Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
On-chip heterogeneous processors face issues such as high power density and power integrity problems, insufficient capacitance density of coupling capacitors, and bandwidth limitations in graphics processing units, along with increased computation pressure in neural network processing units.
Innovation Solution
A chip design comprising a first chip component with processor units and a second chip component with integrated passive devices and memories, where the passive devices are connected to processor units and memories to enhance capacitance density and reduce latency, and the neural network processing unit offloads computation tasks to a processing in memory module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If on-chip heterogeneous processors are used to satisfy complex mobile application requirements, then processing capability is improved, but power density and power integrity problems worsen
Solution Approach 1:
The chip is divided into multiple chip components, each containing processor units, integrated passive devices, and memories. This segmentation allows distributed power management and reduces power density concentration in any single region, while maintaining overall high processing capability across the heterogeneous processor system.
Solution Approach 2:
Integrated passive devices are introduced as intermediary elements between processor units and memories. These passive devices improve power integrity by providing local decoupling and filtering, thereby mitigating power density issues without compromising the processing capability of the heterogeneous processors.
2Productivity
If on-chip heterogeneous processors are used to satisfy complex mobile application requirements, then processing capability is improved, but capacitance density of coupling capacitors becomes insufficient
Solution Approach 1:
The patent merges integrated passive devices with memories within the same chip component. This combination increases the effective capacitance density by integrating decoupling capacitors and other passive elements alongside memory structures, thereby supporting high-speed heterogeneous processing without requiring separate capacitor regions.
Solution Approach 2:
The design transitions from planar capacitor布局 to three-dimensional integration by stacking chip components vertically. This dimensional change enables higher capacitance density by utilizing vertical space for capacitor structures and interlayer coupling, thus supporting enhanced processing capability without increasing footprint area.
3Speed
If bandwidth capacity is increased to meet graphics processing unit demands, then data transfer speed is improved, but latency for data storage and reading increases
Solution Approach 1:
The patent implements cache memory structures within chip components that pre-load and store frequently accessed data. This preliminary action reduces the need for repeated high-bandwidth data transfers from main memory, thereby maintaining high data transfer speeds while reducing average access latency through localized caching.
Solution Approach 2:
The design employs a nested memory hierarchy with multiple levels of caching integrated within chip components. Small, fast caches are nested within larger, slower memory structures, enabling quick access to frequently used data while maintaining high bandwidth capacity for bulk data transfers, thus balancing speed and latency requirements.
4Use of energy by moving object
If computation pressure is reduced in neural network processing units, then energy consumption is lowered, but computing capability may be compromised
Solution Approach 1:
The patent extracts specific computation tasks from neural network processing units and offloads them to dedicated processing elements within the same chip component. This extraction reduces the computation pressure and energy consumption of the main neural network processor while maintaining overall computing capability through distributed task execution across multiple specialized units.
Data Source
AI summary
A chip includes a first chip component and a second chip component. The first chip component includes one or more processor units. The second chip component includes one or more integrated passive devices and one or more memories. At least one of the integrated passive devices is connected to at least one of the processor units, and at least one of the memories is connected to at least one of the processor units.