Heterogeneous Clock Latency Control for High-Speed DRAM Interfaces
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Solution Overview
Problem
Existing dynamic random-access memory (DRAM) systems face challenges in increasing data interfacing speed while maintaining the operating speed of the core circuit unit, particularly due to limitations in the frequency of the main clock signal applied to the core circuit unit.
Innovation Solution
A memory system that utilizes a toggle signal of a data clock signal as a latency control signal, incorporating a memory controller with a first clock signal generator, a second clock signal generator, a latency controller, and a select circuit to control latency for multiple clock signals, allowing for efficient data output by synchronizing the main and data clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the main clock signal is increased to increase data interfacing speed, then the data transfer rate improves, but the core circuit unit cannot operate at the higher speed due to its design limitations
Solution Approach 1:
The patent divides the clock signal system into two separate domains: a main clock signal domain for controlling the core circuit unit and a data clock signal domain for data input/output operations. This segmentation allows each domain to operate at its optimal frequency independently, enabling high-speed data interfacing without compromising core circuit stability.
Solution Approach 2:
The patent introduces a domain crossing circuit as an intermediary mechanism to transfer data between the main clock domain and the data clock domain. This mediator handles the synchronization and timing adjustments required when data moves between different clock frequency domains, preventing data loss and maintaining system reliability.
2Productivity
If separate clock domains are used for main clock and data clock, then data interfacing speed can be increased independently, but timing synchronization and data loss occur during domain crossings
Solution Approach 1:
The patent employs preliminary actions by generating toggle signals in advance and using them to control the timing of domain crossing operations. The latency controller uses these preliminary signals to prepare the system for upcoming data transfers, ensuring proper timing alignment before actual data movement occurs between clock domains.
Solution Approach 2:
The patent implements feedback mechanisms where the domain crossing circuit monitors the timing relationships between the main clock and data clock domains, and adjusts its operation accordingly. This feedback ensures that data is transferred at the correct moments, maintaining synchronization accuracy despite the frequency difference between domains.
Data Source
AI summary
A memory system that controls latency for a plurality of clock signals and outputs at least one of read data and write data includes a memory controller configured to receive a data output command from a host, generate a plurality of clock signals for outputting data, and control latency of the plurality of clock signals, and an input/output (I/O) circuit configured to output data based on the clock signals having the controlled latency.