Heterogeneous Code Loader Architecture for CPU GPU Relocation
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Solution Overview
Problem
Compiling and executing programs that include instructions for heterogeneous architectures, such as central processing units (CPUs) and graphics processing units (GPUs), is more complex than for programs targeted to a single architecture, requiring improved techniques to efficiently handle multiple architectures.
Innovation Solution
The techniques involve a compiler that generates heterogeneous code objects, which are loaded into specific memories for each architecture, with a loader performing relocations to ensure correct execution across different architectures, including name mangling and heterogeneous function pointer transformations to facilitate cross-architecture functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single loader is used for both CPU and GPU code objects, then device complexity is reduced, but manufacturing precision deteriorates due to architecture-specific loading requirements
Solution Approach 1:
The patent divides the loading process into separate phases: a generic loader performs initial loading and basic relocations, while architecture-specific relocation handlers perform precise address adjustments. This segmentation allows the main loader to remain simple while accuracy is maintained through specialized sub-components.
Solution Approach 2:
The patent introduces architecture-specific relocation handlers as intermediary components between the generic loader and the final execution. These handlers act as mediators that translate generic load information into architecture-specific address mappings, preserving both simplicity and precision.
2Manufacturing precision
If architecture-specific relocation handlers are implemented, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service mechanisms where each architecture-specific relocation handler contains its own logic for performing relocations. The handlers automatically identify their target architecture and execute appropriate relocation routines without external intervention, reducing the burden on the main loader and improving modularity.
Solution Approach 2:
The patent performs preliminary identification of the target architecture during the loading phase, before executing architecture-specific relocations. This preliminary action allows the system to prepare the appropriate relocation handler in advance, ensuring accurate relocations while maintaining a clean separation of concerns.
3Manufacturing precision
If separate loading procedures are used for CPU and GPU, then manufacturing precision is improved, but ease of operation deteriorates
Solution Approach 1:
The patent creates a universal loader that can handle both CPU and GPU code objects through a common interface. The loader uses architecture identification mechanisms to automatically select the appropriate relocation handler, providing a unified loading procedure that maintains precision across different architectures without requiring user intervention.
4Manufacturing precision
If architecture identification is performed during loading, then manufacturing precision is improved, but productivity decreases due to additional processing steps
Solution Approach 1:
The patent performs architecture identification as a preliminary step during the initial loading phase, before executing architecture-specific relocations. By identifying the target architecture early in the process, the system can prepare the appropriate relocation handler in advance, avoiding repeated identification checks and minimizing the impact on loading speed.
Solution Approach 2:
The architecture-specific relocation handlers contain embedded identification logic that automatically detects the target architecture without requiring external queries. This self-service approach eliminates the need for complex architecture detection routines in the main loader, reducing overhead and improving loading efficiency.
Data Source
AI summary
Described herein are techniques for executing a heterogeneous code object executable. According to the techniques, a loader identifies a first memory appropriate for loading a first architecture-specific portion of the heterogeneous code object executable, wherein the first architecture specific portion includes instructions for a first architecture, identifies a second memory appropriate for loading a second architecture-specific portion of the heterogeneous code object executable, wherein the second architecture specific portion includes instructions for a second architecture that is different than the first architecture, loads the first architecture-specific portion into the first memory and the second architecture-specific portion into the second memory, and performs relocations on the first architecture-specific portion and on the second architecture-specific portion.