Heterogeneous Multi-Core Compilation Flow for SoC Routing
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Solution Overview
Problem
Existing compilers for multi-core architectures do not effectively address heterogeneous architectures, particularly multi-core processors coupled with reconfigurable/programmable logic, failing to map compute kernels to processor cores and data structures to memory banks, and route stream data and DMA data efficiently.
Innovation Solution
A compilation flow for a heterogeneous multi-core architecture that involves determining a graph representation of an application, mapping kernels onto data processing engines (DPEs) and data structures onto memory, building a routing graph for communication channels, adding constraints based on the architecture, and routing communication channels between DPEs and programmable logic to generate implementation data for programming the System-on-Chip (SoC).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing compilers are used for multi-core architectures, then compilation is possible, but heterogeneous architectures with reconfigurable logic cannot be effectively addressed
Solution Approach 1:
The compiler is extended to handle multiple architecture types (homogeneous multi-core and heterogeneous architectures with reconfigurable logic) within a single unified toolchain. The system automatically detects the target architecture and applies appropriate compilation strategies, making the compiler universally applicable to diverse SoC configurations without requiring separate compilers for each architecture type.
Solution Approach 2:
The compiler incorporates architecture-specific parameters and configuration options that can be dynamically adjusted based on the target platform. By changing compilation parameters such as memory mapping strategies, routing protocols, and resource allocation policies, the same compiler can optimize code generation for different heterogeneous architectures while maintaining core functionality.
2Productivity
If kernels are mapped to processor cores and data structures to memory banks, then computation can be executed, but efficient routing of stream data and DMA data between components is not achieved
Solution Approach 1:
The compiler performs static routing analysis and generates routing tables during the compilation phase rather than at runtime. By pre-calculating optimal data paths for stream and DMA operations based on the kernel-to-core and data-structure-to-memory mapping, the system eliminates runtime routing delays and enables faster data transmission between components during execution.
Solution Approach 2:
The compiler introduces an intermediate routing layer that mediates between the high-level kernel mapping and the physical data transmission paths. This intermediate layer generates optimized routing instructions and manages DMA channels, acting as a bridge that coordinates data movement efficiently across the heterogeneous architecture without requiring direct manual intervention.
3Manufacturing precision
If a compilation flow is implemented for heterogeneous multi-core architecture, then kernel mapping and data structure allocation can be optimized, but the complexity of the compilation process increases
Solution Approach 1:
The compilation flow is divided into distinct modular phases: architecture detection, kernel-to-core mapping, data-structure-to-memory mapping, routing generation, and code generation. Each phase handles a specific aspect of the compilation process independently, making the overall complex task manageable through sequential processing stages. This segmentation allows each module to be optimized and tested separately while contributing to the final integrated solution.
Solution Approach 2:
The compiler incorporates feedback mechanisms that analyze mapping results and routing configurations in real-time, allowing automatic adjustments to optimize the overall system performance. By evaluating the impact of mapping decisions on data transmission efficiency and resource utilization, the compiler can iteratively refine its outputs to achieve optimal performance while managing complexity through automated optimization loops.
Data Source
AI summary
An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array including determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, building a routing graph of all possible routing choices in the DPE array for communicate channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding constraints to the routing graph based on an architecture of the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC based on the routing graph, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.