Heterogeneous Device Compilation via Intermediary Linking
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Solution Overview
Problem
Current development environments for heterogeneous integrated circuits (ICs) face challenges in efficiently compiling and linking user applications across different subsystems, which are often written in various programming languages and models, leading to complex integration and control of hardware accelerators.
Innovation Solution
A method and system that compile each section of a user application into accelerator representations based on specific programming models and subsystems, link these representations, and generate program code to control hardware accelerators, enabling seamless integration across heterogeneous device platforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If distinct and independent development paths are used for each subsystem, then each subsystem can be developed using its specialized programming model, but the integration and linking complexity increases
Solution Approach 1:
The patent introduces an intermediary linking process that translates between different programming models and subsystem interfaces. This mediator component handles the conversion and coordination between heterogeneous subsystems, allowing each to maintain its specialized programming model while enabling seamless integration without direct complex interactions between subsystems.
Solution Approach 2:
The patent creates a universal interface layer that can accommodate multiple programming models and subsystem types. This universal linking mechanism provides standardized communication protocols and translation capabilities that work across different subsystem architectures, reducing integration complexity while maintaining adaptability to various programming paradigms.
2Adaptability or versatility
If manual compilation and linking processes are used for heterogeneous subsystems, then flexibility in handling different programming models is maintained, but the development time and effort increase
Solution Approach 1:
The patent implements preliminary compilation steps that preprocess each subsystem's code into an intermediate representation before linking. This preliminary action includes generating metadata about interface requirements, data types, and communication protocols, which are then used by the linking process to automatically integrate subsystems, significantly reducing manual effort and development time.
Solution Approach 2:
The patent enables subsystems to self-describe their interface requirements and programming model characteristics through automated metadata generation. Each subsystem automatically provides information about its interfaces, data structures, and communication needs, allowing the linking process to autonomously integrate them without extensive manual configuration or programmer intervention.
3Productivity
If separate development paths are maintained for software and circuit design portions, then each portion can be optimized independently, but the overall system integration becomes more difficult
Solution Approach 1:
The patent divides the development process into distinct segments for software and circuit design, allowing each to be optimized independently using specialized tools and methodologies. The segmentation is maintained through separate compilation processes for each subsystem type, while a unified linking framework integrates these segments into a cohesive system, preserving both independent optimization capability and system-level integration.
Data Source
AI summary
Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator representation. Linking the accelerator representations based on a platform of the heterogeneous device, generating a hardware implementation of the application for the heterogeneous device based on the linked accelerator implementations, and automatically generating program code configured to control one or more of the plurality of hardware accelerators of the hardware implementation.