Heterogeneous Compute Domain with Embedded OS for Out-of-Band Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing information handling systems face limitations in accommodating large BIOS/UEFI code due to size constraints of SPI ROM, leading to difficulties in including advanced firmware features and requiring elaborate recovery procedures, with no efficient mechanism for out-of-band management and parallel operation of host and embedded OS.
Innovation Solution
The implementation of a chipset with a main processor and a hybrid processor, allowing for a heterogeneous compute domain with separate memory mappings and OS loading during pre-boot phases, enabling independent operation of host and embedded OS and providing a System Management Interrupt (SMI) mechanism for inter-processor communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If BIOS/UEFI code size is increased to include advanced firmware features, then firmware functionality is improved, but SPI ROM capacity is exceeded
Solution Approach 1:
The system divides firmware into two separate components: traditional BIOS/UEFI firmware stored in SPI ROM and an embedded operating system stored in a larger memory device. This segmentation allows each component to be optimized independently, with the embedded OS providing extended functionality without consuming SPI ROM capacity.
Solution Approach 2:
The patent extracts the operating system from the traditional BIOS/UEFI firmware image and places it in a separate memory device. This extraction removes the size constraint imposed by SPI ROM, allowing the firmware functionality to expand significantly while the SPI ROM retains only the essential boot firmware.
2Adaptability or versatility
If single processor architecture is used, then system simplicity is maintained, but out-of-band management capability is lost
Solution Approach 1:
The system segments processing responsibilities by introducing a hybrid processor alongside the main processor. The hybrid processor handles out-of-band management tasks while the main processor handles host operations, allowing both functionalities to operate independently without interfering with each other.
Solution Approach 2:
The hybrid processor acts as an intermediary between the host system and management functions. It provides a separate execution environment that can manage system resources and perform out-of-band operations without requiring the host operating system to be running, thus enabling management capabilities while maintaining relative architectural simplicity.
3Ease of repair
If host OS is down, then system recovery is needed, but serviceability is reduced
Solution Approach 1:
The embedded operating system is pre-loaded into a memory device during system initialization, before the host operating system boots. This preliminary action ensures that the embedded OS is ready to immediately take over management functions if the host OS fails, enabling continuous serviceability without requiring full system recovery procedures.
Solution Approach 2:
When the host OS fails, the system recovers by transferring control to the embedded operating system rather than requiring a complete system recovery. The embedded OS can independently manage system resources and facilitate recovery operations, maintaining serviceability even when the primary host OS is unavailable.
Data Source
AI summary
An information handling system includes a memory device, a memory, a chipset, and a basic input/output system (BIOS). The chipset includes a main processor and a hybrid processor. During a first pre-boot phase, the BIOS memory maps the hybrid processor to a first portion of the memory device, and stores an embedded operating system in the memory. During a second pre-boot phase, the BIOS memory maps the main processor to a second portion of the memory device, stores a host operating system in the memory, and loads the embedded operating system on the hybrid processor. The second portion is a larger portion of the memory device than the first portion.