Heterogeneous Compute Platform Layout for Low-Power Network Functions

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Solution Overview

Problem

The challenge of maintaining a cost and power-efficient computing infrastructure to support the doubling of internet traffic every two years, as the density of transistors within the same sized Integrated Circuit (IC) no longer doubles, leading to an imbalance in supply and demand for high bandwidth, low latency, and secure network functions.

Innovation Solution

A modular compute platform architecture that supports either Arm or x86 based CPUs, with optional L1 processors, leveraging an infrastructure processing unit (IPU) for efficient deployment of network functions, including virtualized units (vDU and vCU) and accelerators for high-performance, low-power operation, and secure connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If general purpose processors (GPP) are used to host network functions, then versatility and ease of deployment are improved, but power consumption and cost efficiency deteriorate

Engineering Contradiction:

ImproveversatilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent segments the processing architecture into heterogeneous components: general purpose processors (GPP) for control plane functions and infrastructure processing units (IPU) for data plane functions. This segmentation allows each processor type to be optimized for its specific workload, improving overall power efficiency while maintaining versatility through the combination of different processing capabilities.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The IPU is designed with multi-functionality to handle various data plane processing tasks including packet forwarding, network address translation, and security functions. This universal capability within the IPU reduces the need for specialized hardware while maintaining power efficiency, thereby resolving the contradiction between versatility and power consumption.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If transistor density is increased to meet growing traffic demand, then processing capacity is improved, but power footprint and cost efficiency worsen

Engineering Contradiction:

Improveprocessing capacityVSAvoidpower footprint

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The patent applies local quality by assigning different processing capabilities to different components: GPP for control functions and IPU for data plane functions. The IPU is specifically optimized with local quality enhancements for high-speed packet processing and network address translation, achieving high processing capacity in specific areas without proportionally increasing overall power footprint.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The architecture changes the processing parameters by introducing IPU with optimized instruction sets and processing modes for data plane functions. This parameter change enables efficient handling of high-volume traffic with lower power consumption compared to using GPP for the same tasks, thus improving productivity while controlling power footprint.

Inventive Principle:

Principle #35Parameter changes

3Speed

If lookaside or inline acceleration building blocks are added to offload compute intensive processing, then processing speed is improved, but device complexity worsens

Engineering Contradiction:

Improveprocessing speedVSAvoiddevice complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent merges the acceleration functions into the IPU itself, combining packet processing, network address translation, and security functions in a single integrated unit. This merging reduces device complexity compared to having separate lookaside or inline acceleration building blocks, while maintaining high processing speed through the unified architecture.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The IPU acts as an intermediary between the GPP and the network interface, handling compute-intensive data plane functions that would otherwise require separate acceleration hardware. This intermediary role eliminates the need for additional complex acceleration building blocks while maintaining processing speed through efficient IPU design.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12530309B2Heterogeneous compute platform architecture for efficient hosting of network functions

Publication Date: 2026.01.20 GOOGLE LLC

AI summary

The present disclosure provides for a converged compute platform architecture, including a first infrastructure processing unit (IPU)-only configuration and a second configuration wherein the IPU is coupled to a central processing unit, such as an x86 processor. Connectivity between the two configurations may be accomplished with a PCIe switch, or the two configurations may communicate through remote direct memory access (RDMA) techniques. Both configurations may use ML acceleration through a single converged architecture.