Heterogeneous Computing System for Video Algorithm Acceleration
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Solution Overview
Problem
Conventional heterogeneous computing systems face challenges in efficiently processing image algorithms for display systems, including long pre-processing times, image compression loss, and complex hardware-software integration, especially when modifications are needed, which hinders real-time processing and effective noise observation in static images.
Innovation Solution
A heterogeneous computing system comprising an interrupt processing unit, an FPGA unit, an image input unit, a system memory unit, and a central processing unit, which simplifies the development schedule and resource usage by enabling synchronous processing and rapid verification of image algorithms, with a display device connected for real-time image processing and output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GPU or NPU is used for universal parallel operations, then processing capability is improved, but synchronous process cannot be performed effectively and development complexity increases
Solution Approach 1:
The system divides the computing task into three distinct segments: image data inputting (CPU), processing (FPGA), and outputting (CPU). This segmentation allows each component to specialize in specific functions, enabling effective synchronous processing while reducing overall development complexity compared to using a single GPU/NPU for all operations.
Solution Approach 2:
The FPGA unit serves as an intermediary between the CPU and the display device, specifically handling the image processing function. This intermediary approach allows the CPU to focus on data input/output while the FPGA handles synchronous processing, resolving the contradiction between processing capability and development complexity.
2Speed
If FPGA hardware acceleration mode is used, then processing speed is improved, but more manpower and time are required to integrate hardware and software systems
Solution Approach 1:
The FPGA unit is designed with universal functionality to handle various image processing algorithms while maintaining a standardized interface with the CPU and display device. This multi-functionality reduces the need for custom integration work for each algorithm, thereby reducing integration time while maintaining high processing speed.
Solution Approach 2:
The system allows dynamic adjustment of processing parameters (such as image quality enhancement levels, processing resolution) without requiring hardware reconfiguration or reintegration. This parameter-based flexibility reduces integration time while maintaining the speed advantage of FPGA hardware acceleration.
3Difficulty of detecting and measuring
If static images are displayed dynamically, then noise observation is enabled, but long pre-processing time and image compression loss occur
Solution Approach 1:
The FPGA unit performs preliminary processing actions on image data in real-time as it is input from the CPU, preparing the data for display without requiring long pre-processing intervals. This preliminary action enables noise observation in static images while minimizing pre-processing time through continuous background processing.
Solution Approach 2:
The system maintains continuous useful action by keeping the FPGA unit actively processing image data in real-time, rather than performing batch processing. This continuity enables smooth noise observation in static images while eliminating long pre-processing delays, as the processing pipeline operates continuously without interruption.
Data Source
AI summary
A heterogeneous computing system and a heterogeneous computing method using the system are provided and capable of executing accelerating running of a video algorithm. Furthermore, the heterogeneous computing system decreases the complexity of hardware design and the use of resources by pre-processing and simple operations. Furthermore, the required time for adjusting processes of software and hardware of the heterogeneous computing system can be efficiently decreased.