Heterogeneous Controller and Cache Stacked with Continuous TSVs
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Solution Overview
Problem
The increasing number of memory layers in 3D memory structures for datacenters poses challenges in positioning the logic circuit beneath the memory cell structure, with heat from fabrication steps adversely affecting the logic circuit's operation, and existing TSV technologies require multiple complex processes.
Innovation Solution
A semiconductor device with a controller die and memory array dies stacked using continuously formed through-silicon vias (TSVs), which can be configured in face-up or face-down orientations, omitting processes like via etching and seed layer deposition, and integrating ASIC logic circuits for memory management and cache structures to improve access times and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory layers in 3D memory structures is increased to meet datacenter memory demands, then storage capacity is improved, but it becomes harder to position the logic circuit beneath the 3D memory cell structure
Solution Approach 1:
The patent transitions from a traditional planar configuration where logic circuits are positioned beneath memory cells to a three-dimensional stacked architecture. Memory array dies are stacked vertically above controller dies using through-silicon via (TSV) technology, enabling high-density storage while maintaining logical circuit functionality in a separate dimensional plane.
Solution Approach 2:
The semiconductor device is divided into functionally independent modules: controller dies containing logic circuits and cache structures, and separate memory array dies containing memory cells. This segmentation allows each module to be optimized independently and stacked vertically, resolving the positioning conflict between logic circuits and high-density memory layers.
2Manufacturing precision
If heat is applied to the 3D memory cell structure in fabrication steps, then memory cell structure formation is improved, but the logic circuit operation is adversely affected
Solution Approach 1:
The fabrication process is segmented into separate thermal processing stages: memory array die formation with high-temperature steps to create memory cell structures, followed by controller die fabrication with lower-temperature processes for logic circuits. This temporal and spatial separation of thermal processes allows optimization of memory cell formation without damaging sensitive logic circuit components.
Solution Approach 2:
Different thermal processing conditions are applied to different regions and stages of fabrication. High-temperature processing is localized to memory array die formation where it is needed for memory cell structure creation, while controller die fabrication uses controlled lower temperatures appropriate for logic circuit components, ensuring each region receives optimal thermal treatment.
3Reliability
If existing TSV technologies are used for stacking, then memory array dies can be connected to controller dies, but multiple complex processes are required including via etching and seed layer deposition
Solution Approach 1:
Through-silicon via structures are pre-formed during the individual die fabrication process before stacking. The TSV openings, liners, and conductive fills are created as integral parts of the controller die and memory array die manufacturing, so that when dies are stacked and bonded, electrical connections are immediately established without requiring additional via etching or seed layer deposition steps.
Solution Approach 2:
The TSV fabrication process is merged with the standard CMOS fabrication流程 for both controller dies and memory array dies. The via formation, insulation layer deposition, and conductive material filling are combined with the existing fabrication sequence, eliminating the need for separate post-stack TSV processing steps and reducing overall process complexity.
Data Source
AI summary
A semiconductor device is disclosed including a controller die and a memory module. The controller die may be a heterogeneous integrated controller die having ASIC logic circuits, memory array logic circuits and a cache structure. In examples, the memory module may have continuously formed through silicon vias in a face-up or face-down configuration.