Heterogeneous Core Memory Frequency Scaling
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Solution Overview
Problem
Complex computer systems with heterogeneous processing cores face challenges in optimally balancing memory frequency to achieve both performance and power savings, as existing Dynamic Voltage and Frequency Scaling (DVFS) techniques lack sophistication in managing diverse core types and their varying bandwidth and latency needs.
Innovation Solution
Implementing a frequency optimization algorithm that differentiates frequency adjustments based on the type of core requesting bandwidth and response, increasing frequency more generously for high-performance cores and more sparingly for energy-efficient cores, while also considering the source of previous frequency requests to balance performance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory frequency is increased to improve performance, then bandwidth and latency are improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating frequency adjustment policies based on core type. High-performance cores receive larger frequency increments when requesting bandwidth, while energy-efficient cores receive smaller increments. This localized differentiation resolves the contradiction by optimizing frequency allocation according to specific core requirements rather than applying a uniform policy, thereby improving performance when needed while conserving power when sufficient performance already exists.
Solution Approach 2:
The patent implements dynamics through its frequency optimization algorithm that dynamically adjusts memory frequency based on real-time requests from different core types. The system continuously monitors bandwidth requests and adapts frequency levels accordingly, increasing frequency more aggressively for high-performance cores and more conservatively for energy-efficient cores. This dynamic adjustment resolves the contradiction by matching frequency levels to actual performance needs rather than maintaining static frequency settings.
2Adaptability or versatility
If a uniform frequency adjustment policy is applied to all cores, then implementation is simple, but it fails to optimally balance performance and power for heterogeneous core types
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through differentiated frequency adjustment policies for different core types. The algorithm identifies whether a request comes from a high-performance core or an energy-efficient core and applies appropriate frequency increment strategies. This approach provides the adaptability needed for heterogeneous architectures while maintaining reasonable algorithmic complexity through clear differentiation rules rather than overly complex decision-making logic.
Solution Approach 2:
The patent applies parameter changes by modifying the frequency adjustment parameter based on core type. When a high-performance core requests bandwidth, the system applies a larger frequency increment parameter. When an energy-efficient core requests bandwidth, a smaller increment parameter is applied. This parameter differentiation enables the system to adapt to different core types while keeping the algorithm structure relatively simple, resolving the contradiction between adaptability and complexity.
Data Source
AI summary
Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to optimizing memory frequency based on the bandwidth and latency needs of heterogeneous processing cores in a computer system. According to various embodiments, adjustments to the frequency of memory may be applied differently depending on the type of core requesting more bandwidth and/or faster response. According to various embodiments, the frequency is increased more sparingly for energy-efficient cores, while the frequency is increased more generously for high-performance cores. Additionally, when memory traffic decreases, the frequency of memory is decreased more generously when the previous request for higher frequency was from an energy-efficient core than a high-performance core. By considering the type of core that is requesting more bandwidth and/or faster response, performance and power consumption may be more optimally balanced.