Heterogeneous Core Processor Runtime Code Optimization
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Solution Overview
Problem
Current processors with heterogeneous cores face challenges in optimizing execution of applications due to shared instruction set architecture, leading to inefficient processing and increased power consumption, as high-performance and low-power cores are not effectively utilized based on their specific features.
Innovation Solution
An operation method for a processor with multiple heterogeneous cores that selects the appropriate core for executing applications by loading compile data specific to each core's features, profiling execution codes, and modifying execution codes to refer to optimized functions for each core, thereby improving processing speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a shared instruction set architecture is used for heterogeneous cores, then compatibility and ease of operation are improved, but processing speed and power efficiency deteriorate due to inability to optimize for specific core features
Solution Approach 1:
The patent segments the application code into multiple versions, each optimized for specific heterogeneous core types. The system divides the monolithic instruction set into core-specific variants, allowing each core to execute optimized code while maintaining overall system compatibility through the segmentation of functionality.
Solution Approach 2:
The patent applies local quality by providing different optimized code versions for different core types within the heterogeneous processor. Each core receives locally optimized instructions tailored to its specific architectural features, while the overall system maintains a unified interface through the shared instruction set architecture.
2Ease of operation
If a shared instruction set architecture is used for heterogeneous cores, then ease of operation is improved, but power consumption increases due to inefficient processing
Solution Approach 1:
The system segments power consumption optimization by creating separate code paths for different core types. Each segment is optimized for the specific power characteristics of its target core, allowing the system to minimize power usage by executing the appropriate segmented code on each core type.
Solution Approach 2:
The patent changes the parameter of code optimization by generating different versions of the same functionality with parameters tuned for specific core types. This allows power consumption to be optimized by selecting and executing parameter-appropriate code versions for each heterogeneous core.
3Ease of operation
If generic code is executed on heterogeneous cores, then ease of operation is improved, but code duplication and waste increase
Solution Approach 1:
The patent uses selective copying by creating copies of code segments only when and where they are needed for specific core types. Rather than duplicating entire codebases, the system copies and optimizes only the necessary functional segments for each heterogeneous core, minimizing redundant code while maintaining portability.
Data Source
AI summary
Provided is an operation method of a processor including a plurality of heterogeneous cores, the operation method including selecting an execution core of the plurality of heterogeneous cores for executing an application, loading, from a memory, first data corresponding to core information of the execution core during runtime of the execution core, wherein the first data is included in compile data, the compile data including a first function compiled for each heterogeneous core of the plurality of heterogeneous cores, the first function being a function from among a plurality of functions of the application that is at least one of frequently called or having a long execution time, and processing, by the execution core, execution codes for executing the application, based on the first data.