Heterogeneous CPU Cluster for Real-Time Event Processing
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Solution Overview
Problem
Existing electronic computing devices for industrial control units face challenges in balancing high load applications with real-time constraints, power consumption, and cost, particularly in autonomous systems that require both periodic and event-driven processing with varying loads.
Innovation Solution
An electronic computing device with a heterogeneous configuration of high-performance and low-performance CPU clusters, a DMA controller, and an accelerator, where periodic processing is allocated to high-performance cores and event-driven processing to low-performance cores, with the accelerator managing specific processing tasks to optimize resource utilization and reduce interrupt overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-core or many-core processor with peripheral resources is used to handle high load applications, then computing performance is improved, but device complexity and power consumption increase
Solution Approach 1:
The system segments computing tasks into periodic processing and event-driven processing, allocating them to different core types. High-performance cores handle periodic processing while low-performance cores handle event-driven processing, reducing overall device complexity and power consumption while maintaining computing performance.
Solution Approach 2:
The system applies local quality by using heterogeneous cores with different performance characteristics suited for different task types. High-performance cores are used where high computing power is needed for periodic processing, while low-performance cores suffice for event-driven processing, optimizing the balance between performance and complexity.
2Productivity
If high-performance cores are used for all processing tasks, then computing efficiency is improved, but power consumption increases
Solution Approach 1:
The system segments processing tasks by type (periodic vs. event-driven) and assigns them to appropriate core performance levels. This segmentation allows low-performance cores to handle event-driven processing, reducing power consumption while high-performance cores maintain computing efficiency for periodic processing.
Solution Approach 2:
The system changes the performance parameter of CPU cores by providing a range of performance levels (high-performance and low-performance cores). This allows the system to match core performance to task requirements, improving computing efficiency where needed while minimizing power consumption elsewhere.
3Speed
If interrupt processing is used for event-driven processing, then real-time response is improved, but processing overhead increases
Solution Approach 1:
The system segments event-driven processing from periodic processing and assigns event-driven tasks to low-performance cores. This segmentation reduces the interrupt overhead on high-performance cores while maintaining real-time response through dedicated event handling on low-performance cores.
Solution Approach 2:
The system introduces an intermediary mechanism where low-performance cores act as mediators for event-driven processing. These cores handle interrupts and event processing, reducing the processing overhead on high-performance cores while maintaining real-time response capabilities.
4Productivity
If resource allocation is optimized for periodic processing, then throughput is improved, but real-time response to events may be delayed
Solution Approach 1:
The system segments processing into two distinct categories handled by different core types: periodic processing on high-performance cores for high throughput, and event-driven processing on low-performance cores for real-time response. This segmentation resolves the contradiction by providing dedicated resources for each processing type.
Solution Approach 2:
The system applies local quality by assigning different processing qualities to different task types. High-performance cores provide high throughput for periodic processing, while low-performance cores provide responsive event handling. Each core type is optimized for its specific function, resolving the throughput-response tradeoff.
Data Source
AI summary
The computing efficiency of an electronic computing device is improved. HPCs 20 to 23 include arithmetic processing units HA0 to HA3, respectively. Each of the arithmetic processing units HA0 to HA3 executes arithmetic processing in parallel. LPCs 30 to 33 includes management processing units LB0 to LB3, respectively. Each of the management processing units LB0 to LB3 manages execution of specific processing by an accelerator 6 when each of the arithmetic processing units HA0 to HA3 causes the accelerator 6 to execute the specific processing, and performs a series of commands for causing the accelerator 6 to execute the specific processing on a DMA controller 5 and the accelerator 6.