Heterogeneous Data Processing Unit for Wireless Baseband
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Solution Overview
Problem
Existing wireless communications systems face challenges in efficiently processing high-speed baseband signals due to power consumption and complexity issues when implementing baseband processing at GHz frequencies, particularly in small, low-power devices, and existing solutions either consume excessive power or lose flexibility in processing algorithms.
Innovation Solution
A data processing unit comprising a scalar processor and a heterogeneous processor device with a vector processor array, LDPC accelerator, and FFT accelerator, utilizing a shared memory resource and common instruction set, which allows for efficient processing by distributing workload across multiple processing units and optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If baseband processing circuitry is operated at high speed (equal to or greater than sample rate), then processing performance is improved, but power consumption becomes excessive
Solution Approach 1:
The patent divides baseband processing into multiple discrete stages (e.g., FFT stage, decoding stage, modulation stage), with each stage implemented as a separate hardware block. This segmentation allows each block to operate at lower individual speeds while collectively achieving the required overall processing throughput, thereby reducing power consumption compared to a single high-speed processor.
Solution Approach 2:
The patent employs dynamic resource allocation where processing resources are activated and deactivated based on real-time traffic conditions and processing requirements. This dynamic approach allows the system to scale power consumption according to actual workload, avoiding continuous operation at maximum speed and thus reducing overall power consumption while maintaining processing performance.
2Productivity
If processing is decomposed into a large number of hardware stages, then processing performance is improved, but power consumption in data movement increases
Solution Approach 1:
The patent combines multiple processing functions into integrated hardware blocks that perform multiple operations within the same stage. For example, a single hardware block may simultaneously perform FFT computation and data reordering, eliminating the need for separate stages and reducing data movement between stages, thereby reducing power consumption associated with data transfer.
Solution Approach 2:
The patent introduces shared memory structures and buffer management mechanisms that serve as intermediaries between processing stages. These intermediaries optimize data movement by implementing intelligent caching, prefetching, and data coalescing strategies, reducing the frequency and volume of data transfers between stages and thereby reducing power consumption.
3Productivity
If processing is decomposed into multiple hardware stages, then processing performance is improved, but flexibility in processing algorithms is lost
Solution Approach 1:
The patent designs hardware processing blocks with universal interfaces and configurable parameters that allow them to perform multiple different processing functions. For example, a decoding block can be reconfigured to handle different coding schemes (convolutional, Turbo, LDPC) through programmable control logic, maintaining algorithmic flexibility while preserving the benefits of hardware acceleration.
Solution Approach 2:
The patent implements dynamically reconfigurable processing blocks that can change their operation mode based on incoming data characteristics and system requirements. This dynamic adaptability allows the same hardware stage to perform different processing algorithms as needed, combining the speed of hardware processing with the flexibility of software-controlled algorithm selection.
4Productivity
If parallel processing with multiple processors is used, then processing performance is improved, but hardware overhead for instruction fetch and issue becomes large
Solution Approach 1:
The patent merges the control logic of multiple processing units into a single centralized controller that manages all processor elements. This unified control architecture eliminates the need for each processor to have independent instruction fetch and issue hardware, significantly reducing the overall hardware overhead while maintaining parallel processing performance through coordinated control of all processing elements.
Data Source
AI summary
A data processing unit combines a scalar processor and a heterogeneous processor which includes a vector processing array. The vector processing array includes a plurality of vector processors which are operable in a single instruction multiple data configuration.