Heterogeneous Multi-Core Debug Control Circuit
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Solution Overview
Problem
Debugging heterogeneous multi-core integrated circuits is complex and costly due to the need for multiple debugging apparatuses and sequential testing of processor cores, limiting debug configurations and increasing time and expense.
Innovation Solution
A system and method that includes a debug control circuit with TAP controllers and mode select pins to configure processor cores for various debugging modes, allowing simultaneous or sequential testing of multiple processor cores through a single or multiple debug ports, reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple debugging apparatuses are used to test multiple processor cores simultaneously, then debugging time is reduced, but system complexity and cost increase
Solution Approach 1:
The patent implements a universal debugging apparatus that can debug multiple types of processor cores (ARM, DSP, GPU, etc.) through a single interface. The TAP controller is designed to be heterogeneous, supporting multiple core types simultaneously, eliminating the need for separate debugging apparatuses for each core type while reducing overall system complexity and cost
2Productivity
If multiple debugging apparatuses are connected to multiple debug ports for simultaneous testing, then debugging efficiency improves, but cost increases
Solution Approach 1:
The patent merges multiple debugging functions into a single debugging apparatus. The TAP controller integrates the capability to handle multiple processor cores and multiple debug protocols within one unit, allowing a single apparatus to perform what previously required multiple separate apparatuses, thereby reducing cost while maintaining high debugging efficiency
3Measurement precision
If a debugging apparatus is designed for a specific processor core type, then debugging precision for that core type is high, but adaptability to other core types is limited
Solution Approach 1:
The TAP controller is designed with universal adaptability to support multiple processor core types including ARM, DSP, GPU, and other heterogeneous cores. It implements multiple debug protocols and interfaces within a single controller, maintaining high debugging precision for each specific core type while providing broad adaptability across different architectures
Data Source
AI summary
A heterogeneous multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. A debug control circuit is connected between the first and second TAP controllers and the first and second debug ports. Based on external configuration signals, the debug control circuit configures the connections between the first and second TAP controllers and the first and second debug ports according to predetermined configuration modes, which allows flexibility in debugging the heterogeneous multi-core integrated circuit.