Heterogeneous Die Packaging with Backside Power Rail Bonding
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Solution Overview
Problem
As semiconductor devices become increasingly complex and densely packed, existing packaging methods struggle to accommodate diverse technology nodes and provide flexible interconnect schemes, leading to challenges in thermal management, mechanical protection, and electrical connectivity.
Innovation Solution
The proposed package device features top dies with interconnect structures that allow for heterogeneous integration, using fusion bonding and metal-to-metal bonding with contact pads, and incorporates a support substrate for structural integrity, enabling flexible configuration and efficient power routing through backside interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If heterogeneous die structures with different technology nodes are integrated, then manufacturing flexibility and adaptability are improved, but device complexity and packaging difficulty increase
Solution Approach 1:
The package device is segmented into multiple top dies (first top die, second top die) with different technology nodes that can be independently fabricated and then integrated. Each die can be manufactured using optimized processes for its specific technology node, allowing manufacturing flexibility while managing complexity through modular assembly
Solution Approach 2:
The package substrate provides universal functionality by accommodating different types of dies (first top die, second top die, third top die) with different technology nodes and interconnect requirements. The substrate's multi-layer interconnect structure and bonding interfaces are designed to universally support heterogeneous integration
2Productivity
If die size and integration density are increased, then productivity and component integration are improved, but thermal management and mechanical stress become more difficult
Solution Approach 1:
The package structure transitions from planar integration to three-dimensional stacking, with top dies positioned over the package substrate at different vertical levels. This vertical arrangement increases integration density while distributing thermal loads across multiple surfaces, improving heat dissipation pathways
Solution Approach 2:
The package substrate acts as an intermediary between the top dies and the underlying support structure, providing thermal management pathways. The substrate's interconnect layers and bonding interfaces serve as thermal conduction paths that distribute and dissipate heat from the densely packed dies
3Reliability
If multiple interconnect structures are implemented for power routing, then electrical connectivity is improved, but manufacturing precision and alignment requirements increase
Solution Approach 1:
Interconnect structures are pre-formed within the package substrate before die attachment. The multi-layer interconnect pattern is established in advance, with bonding pads and conductive paths prepared for subsequent die bonding. This preliminary preparation reduces alignment complexity during assembly
Solution Approach 2:
The package substrate's interconnect layers serve as intermediaries that provide robust electrical pathways between different top dies. The multi-layer structure with embedded conductors creates redundant and reliable connection paths that tolerate minor alignment variations during die bonding
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances manufacturing flexibility, improves thermal management, and ensures reliable electrical connectivity by allowing different technology nodes and redistribution schemes, while providing structural support and efficient power distribution within the densely packed semiconductor devices.
Implementation Method 1
bonding the top interconnect structure to a support substrate
Implementation Method 2
metal-to-metal bonding with contact pads
Data Source
AI summary
A package device includes a top die having a top interconnect structure on a first surface of a transistor layer and a bottom interconnect structure on a second surface of the transistor layer. One of the top interconnect structure or the bottom interconnect structure is direct bonded onto a bottom die. The bottom interconnect structure includes a power rail which directly contacts transistor contacts that are directly contacting a transistor structure in the transistor layer.