Heterogeneous Die Stacking with Post-Bond Thinning

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Solution Overview

Problem

Current techniques for stacking heterogeneous dies, such as pick and place, require dies to be of sufficient thickness, leading to electrical performance issues due to stress field changes and high manufacturing costs for through-silicon vias (TSVs), with a risk of the entire package failing if one die fails, resulting in lower yield.

Innovation Solution

The method involves sorting and bonding known good IC dies from one wafer to known good dies on another, thinning the first dies while bonded, and using a dielectric material with matching mechanical properties to prevent stress field alteration, allowing for efficient stacking of dies of different diameters and reducing TSV complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pick and place techniques are used to stack heterogeneous dies, then dies can be coupled tightly, but dies must be of sufficient thickness which causes electrical performance drift due to stress field changes

Engineering Contradiction:
Improveelectrical performanceVSAvoiddie thickness
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent changes the thickness parameter of the die from a fixed sufficient thickness to a thinned configuration. By performing thinning operations after bonding the die to the substrate, the die can be reduced to a thinner profile without compromising electrical performance, thus resolving the contradiction between maintaining electrical performance and reducing die thickness.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If through-silicon vias (TSVs) are used in dies, then electrical connections can be established, but manufacturing cost increases due to etching and plating of high aspect ratio TSVs

Engineering Contradiction:
Improveelectrical connectionVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the aspect ratio parameter of the TSVs by thinning the die after bonding. This reduces the depth of the TSVs relative to the die thickness, creating lower aspect ratio TSVs that are less expensive to manufacture through etching and plating processes, while still maintaining the necessary electrical connections.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If heterogeneous dies are stacked tightly, then functionality increases, but yield decreases because the entire package fails if either die fails

Engineering Contradiction:
ImprovefunctionalityVSAvoidyield
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the functional units by stacking heterogeneous dies with different functionalities. This allows independent optimization and testing of each die type, enabling better yield management where individual die types can be screened and selected based on their specific performance characteristics before assembly into the final stacked package.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary substrate that bonds multiple heterogeneous dies together. This substrate acts as a mediator that allows for independent handling, testing, and selection of each die type, facilitating yield improvement through selective assembly of known-good dies while maintaining the functional benefits of heterogeneous stacking.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Length of moving object

If die thickness is reduced to enable thinner electronics, then device thinness improves, but stress field changes cause electrical performance drift

Engineering Contradiction:
Improvedevice thicknessVSAvoidelectrical performance
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent performs the thinning operation as a preliminary action after bonding but before final device assembly. By thinning the die at this stage, the stress fields are allowed to stabilize in the thinned configuration, and the die can be subsequently handled and assembled without experiencing stress-induced electrical performance drift, thus achieving both thinness and reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11222863B2Techniques for die stacking and associated configurations
Publication Date: 2022.01.11 INTEL CORP
  • US11222863B2 patent drawing
  • US11222863B2 patent drawing
  • US11222863B2 patent drawing

AI summary

Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed.