Heterogeneous eDRAM Cache Layout for Speed, Area, and Standby Power
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Solution Overview
Problem
The area and standby power challenges of large SRAM-based caches in System on a Chip (SoC) designs are significant, especially for applications requiring large on-die caches, while existing eDRAM-based caches can be further improved for better performance.
Innovation Solution
The eDRAM memory cells are embedded in higher metal layers with the memory peripheral circuits located below the memory array, reducing footprint and latency, and integrating both SRAM and eDRAM in the same IC with heterogeneous memory devices to optimize performance and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM-based cache is used to provide fast data access, then access speed is improved, but area consumption and standby power increase significantly
Solution Approach 1:
The cache is segmented into two distinct arrays: a first array implementing gain cells for frequently accessed data and a second array implementing 1T1C eDRAM cells for less frequently accessed data. This segmentation allows the system to maintain fast access speeds for hot data while using lower-density, lower-power eDRAM for cold data, thereby reducing overall area consumption compared to a fully SRAM-based cache.
Solution Approach 2:
Different quality characteristics are applied to different regions of the cache. The first array uses gain cells with higher read/write speed and lower latency for locally critical data access patterns, while the second array uses eDRAM with lower power consumption and lower cost for less critical data. This local differentiation optimizes the trade-off between speed and area/power consumption.
2Speed
If SRAM-based cache is used to provide fast data access, then access speed is improved, but standby power consumption increases
Solution Approach 1:
The cache is segmented into two distinct arrays: a first array implementing gain cells for frequently accessed data and a second array implementing 1T1C eDRAM cells for less frequently accessed data. This segmentation allows the system to maintain fast access speeds for hot data while using lower-density, lower-power eDRAM for cold data, thereby reducing overall area consumption compared to a fully SRAM-based cache.
Solution Approach 2:
Different quality characteristics are applied to different regions of the cache. The first array uses gain cells with higher read/write speed and lower latency for locally critical data access patterns, while the second array uses eDRAM with lower power consumption and lower cost for less critical data. This local differentiation optimizes the trade-off between speed and area/power consumption.
3Area of stationary object
If eDRAM-based cache is used to reduce area and standby power, then area and power are improved, but access latency increases
Solution Approach 1:
The cache is segmented into two distinct arrays: a first array implementing gain cells for frequently accessed data and a second array implementing 1T1C eDRAM cells for less frequently accessed data. This segmentation allows the system to maintain fast access speeds for hot data while using lower-density, lower-power eDRAM for cold data, thereby reducing overall area consumption compared to a fully SRAM-based cache.
Solution Approach 2:
Different quality characteristics are applied to different regions of the cache. The first array uses gain cells with higher read/write speed and lower latency for locally critical data access patterns, while the second array uses eDRAM with lower power consumption and lower cost for less critical data. This local differentiation optimizes the trade-off between speed and area/power consumption.
4Productivity
If heterogeneous memory devices SRAM and eDRAM are integrated, then computing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges SRAM-based gain cells and eDRAM arrays into a single integrated cache structure with unified control logic. The memory controller manages both array types through a common interface, and the arrays are accessed concurrently based on data access characteristics. This merging approach achieves heterogeneous memory optimization while managing complexity through integrated design rather than separate independent memory subsystems.
Data Source
AI summary
Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. For example, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, and both first and second arrays to store data of a processor. The second plurality of memory cells implements a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit is to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.