Heterogeneous FHE Task Scheduling for Large-Scale Secure Computing
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Solution Overview
Problem
The application of fully homomorphic encryption technology is limited by computing efficiency, especially when processing large-scale data, leading to high computational costs that hinder its use in practical scenarios.
Innovation Solution
A fully homomorphic encryption computing system with a compiler, task scheduler, and heterogeneous processor types, including CPUs, GPUs, and FPGAs, that converts applications into data flow graphs and schedules tasks efficiently across these processors to optimize resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fully homomorphic encryption technology is used to protect data privacy during computation, then data security is improved, but computing efficiency deteriorates due to high computational costs
Solution Approach 1:
The patent segments the computation process into multiple independent tasks represented as a data flow graph, where each node represents a computational operation. This segmentation allows parallel execution of encryption operations across heterogeneous processing modules, reducing the overall computational burden while maintaining security.
Solution Approach 2:
The patent introduces a heterogeneous computing dimension by deploying FHE operations across multiple types of processing modules (CPU, GPU, FPGA, ASIC) with different computational characteristics. This dimensional expansion allows the system to leverage the strengths of each processor type for different computational tasks, improving overall efficiency without compromising security.
2Device complexity
If traditional single-type processors are used for FHE computation, then system simplicity is maintained, but processing capability deteriorates when handling large-scale data
Solution Approach 1:
The patent creates a universal heterogeneous computing platform that can execute FHE operations across multiple processor types (CPU, GPU, FPGA, ASIC). The task scheduler and compiler provide a unified interface that automatically distributes computational tasks to appropriate processing modules based on their capabilities, maintaining system simplicity while maximizing processing capability through multi-functional hardware deployment.
Solution Approach 2:
The patent introduces intermediate software layers (compiler, task scheduler, runtime system) that mediate between the high-level FHE computation and the heterogeneous hardware platform. These intermediaries translate FHE operations into processor-specific instructions and manage resource allocation, allowing complex heterogeneous processing while presenting a simple unified interface to users.
3Device complexity
If FHE operations are executed sequentially on single processors, then resource allocation is simple, but execution time increases significantly
Solution Approach 1:
The patent segments the FHE computation into a data flow graph where nodes represent individual cryptographic operations (encryption, decryption, key generation, arithmetic operations). This segmentation enables the task scheduler to identify independent operations that can be executed in parallel across multiple processing modules, dramatically reducing execution time while the compiler manages the complexity of resource allocation.
Solution Approach 2:
The patent implements continuous parallel execution of FHE operations across heterogeneous processing modules through the data flow graph framework. Multiple encryption and decryption operations proceed simultaneously without idle time, maximizing resource utilization and minimizing execution time while the task scheduler continuously allocates tasks to available processors.
Data Source
AI summary
A fully homomorphic encryption computing method includes: receiving a homomorphic encryption application; converting the homomorphic encryption application into a data flow graph; and performing a resource scheduling on the data flow graph according to connection relationships of a plurality of processing modules and an execution time to produce a scheduled result. The processing modules have at least two heterogeneous processor types.