Heterogeneous-Format Processing Unit for Direct Integer-Floating Arithmetic

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Solution Overview

Problem

Existing floating point units (FPUs) are limited to operating on floating point representation format, necessitating conversion of other data formats, leading to inefficient use of computing resources and increased memory usage, especially in artificial neural networks with mixed data formats.

Innovation Solution

An operator and method that performs binary operations on heterogeneous format inputs, including a multiplier and adder to process integer and floating point formats directly, reducing the need for format conversion and optimizing resource usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If floating point unit converts other data formats to floating point representation format for operation, then operation compatibility is improved, but computing resources are wasted and memory usage increases

Engineering Contradiction:
Improveoperation compatibilityVSAvoidcomputing resources waste
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent implements a dynamic format selection mechanism where the processing device automatically detects the data format of input operands and dynamically switches between floating-point operation mode and integer operation mode. This dynamic adaptation eliminates the need for unnecessary format conversions, allowing the system to operate directly in the most efficient format for each specific computation, thereby reducing computing resource waste while maintaining full operational compatibility across different data formats

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of the processing device by introducing format detection capabilities and configurable operation modes. The system monitors data format parameters (floating-point vs. integer) and adjusts its processing behavior accordingly, enabling it to switch between different computational pathways. This parameter-based control allows the device to optimize resource utilization by selecting the appropriate operation mode based on the actual data formats being processed

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If floating point unit converts other data formats to floating point representation format for operation, then operation compatibility is improved, but device complexity increases

Engineering Contradiction:
Improveoperation compatibilityVSAvoidformat conversion complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a dynamic format selection mechanism where the processing device automatically detects the data format of input operands and dynamically switches between floating-point operation mode and integer operation mode. This dynamic adaptation eliminates the need for unnecessary format conversions, allowing the system to operate directly in the most efficient format for each specific computation, thereby reducing computing resource waste while maintaining full operational compatibility across different data formats

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent extracts the format detection and mode selection functionality as a separate, independent mechanism within the processing device. By isolating the format detection logic and control units that manage mode switching, the system avoids the complexity of universal format conversion circuits. Instead of implementing a complex conversion pathway for all operations, the device extracts and activates only the necessary processing pathway based on detected data formats, simplifying the overall device architecture

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If floating point unit converts other data formats to floating point representation format for operation, then operation compatibility is improved, but operation speed decreases

Engineering Contradiction:
Improveoperation compatibilityVSAvoidoperation speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent implements a dynamic format selection mechanism where the processing device automatically detects the data format of input operands and dynamically switches between floating-point operation mode and integer operation mode. This dynamic adaptation eliminates the need for unnecessary format conversions, allowing the system to operate directly in the most efficient format for each specific computation, thereby reducing computing resource waste while maintaining full operational compatibility across different data formats

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent performs format detection and operation mode selection as a preliminary action before the actual computation begins. By detecting the data formats of input operands and pre-configuring the appropriate operation mode in advance, the system avoids time-consuming format conversions during the computation process itself. This preliminary setup ensures that the processing device is optimally configured for the specific operation type before execution, maximizing operation speed

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250278243A1Processing device using heterogeneous format input
Publication Date: 2025.09.04 REBELLIONS INC
  • US20250278243A1 patent drawing
  • US20250278243A1 patent drawing
  • US20250278243A1 patent drawing

AI summary

A processing device comprises multiplier circuitry configured to output a product of mantissas represented by first and second signals in response to a mode signal and output a product of an integer represented by the first signal and a mantissa represented by the second signal in response to the mode signal. The processing device further includes an aligning circuit configured to shift a mantissa part of a third signal based on an exponent part of the third signal and an exponent of a product of the first and second signal to generate and output a shifted signal. The processing device further includes an arithmetic logic circuit configured to output a mantissa of a sum of a product of the first and second signals and the third signal in response to an output signal of the aligning circuit and an output signal of the multiplier circuitry.