Heterogeneous Gate FET Layout for High- and Low-Voltage Reliability

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Solution Overview

Problem

The challenge of reliably fabricating three-dimensional transistors operating at both high and low voltages in integrated circuit semiconductor elements is becoming increasingly difficult as integration levels increase.

Innovation Solution

The integration of complementary field effect transistors (cFET) with a quadruple-gate structure and fin FETs with triple-gate structures, including nano sheet stacked structures, is implemented on a substrate to enhance reliability and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If three-dimensional transistors are formed with higher integration levels, then device functionality and density are improved, but fabrication reliability deteriorates

Engineering Contradiction:

Improveintegration levelVSAvoidfabrication reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies different gate structure types (planar, fin, zebra fin, GAA) to different regions or devices within the same integrated circuit based on their specific voltage and performance requirements. Low-voltage logic devices use planar or fin structures while high-voltage devices use zebra fin or GAA structures, allowing each device to have optimized local characteristics for its function.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the transistor gate structures into multiple types (planar, fin, zebra fin, GAA) that can be selectively formed in different regions. This segmentation allows the circuit to have both low-voltage and high-voltage devices with appropriate structures, improving overall fabrication reliability by matching structure to function.

Inventive Principle:

Principle #1Segmentation

2Reliability

If heterogeneous gate structures are integrated, then performance and reliability are improved, but device complexity increases

Engineering Contradiction:

Improvedevice reliabilityVSAvoidgate structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs a universal fabrication process framework that can produce multiple gate structure types (planar, fin, zebra fin, GAA) using similar process steps and materials. This multi-functionality allows the same fabrication system to create diverse structures, managing complexity through process standardization while achieving heterogeneous device performance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260020337A1Integrated circuit semiconductor element having heterogeneous gate structures and method of fabricating integrated circuit semiconductor element

Publication Date: 2026.01.15 SAMSUNG ELECTRONICS CO LTD

AI summary

An integrated circuit semiconductor element includes: a substrate; a complementary field effect transistor (FET) (cFET) formed over the substrate and having a quadruple-gate structure, in which nano sheet stacked structures are sequentially stacked; and a planar FET having a mono-gate structure or a zebra fin FET (ZE FINFET) having a triple-gate structure, which are formed over the substrate.