Heterogeneous Gate Structures for Reliable 3D Transistor Integration
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Solution Overview
Problem
The challenge of reliably fabricating three-dimensional transistors operating at both high and low voltages in integrated circuit semiconductor elements is becoming increasingly difficult as integration increases.
Innovation Solution
The integration of complementary field effect transistors (cFETs) with quadruple-gate structures and fin FETs with triple-gate structures, including nano sheet stacked structures, is implemented to form transistors with high reliability on a substrate, utilizing different gate structures for low-voltage logic and high-voltage input/output regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional transistors are formed for high integration, then productivity and integration density are improved, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent applies different gate structure types (planar, fin, zebra fin, cage-like, nanosheet) to different circuit regions based on their specific voltage and performance requirements. Low-voltage logic regions use planar or fin FETs, while high-voltage I/O regions use cage-like or nanosheet FETs with higher gate control. This local differentiation allows each region to be optimized independently, maintaining high integration density while ensuring manufacturing precision and reliability for each specific application.
Solution Approach 2:
The semiconductor device is divided into multiple regions with different gate structures: planar FET regions, fin FET regions, zebra fin FET regions, cage-like FET regions, and nanosheet FET regions. Each region is segmented to handle specific voltage levels and functional requirements. This segmentation allows the complex high-integration device to be manufactured with appropriate precision for each segment, rather than requiring uniform high precision across the entire chip.
2Reliability
If heterogeneous gate structures are used for different voltage regions, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic voltage gating where different gate structures are activated based on operational requirements. The control electrode can selectively apply different voltages to different gate structures (e.g., first voltage to planar FET gates, second voltage to fin FET gates). This dynamic control allows the complex heterogeneous structure to be managed systematically, improving reliability through appropriate voltage application while the control mechanism handles the complexity rather than requiring static complex wiring.
Solution Approach 2:
The patent uses a universal control electrode structure that can simultaneously control multiple types of FETs (planar, fin, zebra fin, cage-like, nanosheet) with different gate configurations. The control electrode serves multiple functions: applying first voltages to some gates, second voltages to other gates, and selectively enabling or disabling different FET types based on operational mode. This multi-functionality reduces the need for separate control circuits for each FET type, managing device complexity while maintaining reliability.
Data Source
AI summary
An integrated circuit semiconductor element includes: a substrate; a complementary field effect transistor (FET) (cFET) formed over the substrate and having a quadruple-gate structure, in which nano sheet stacked structures are sequentially stacked; and a planar FET having a mono-gate structure or a zebra fin FET (ZE FINFET) having a triple-gate structure, which are formed over the substrate.