Automated Hardware Image Generation for Heterogeneous Circuit Designs
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Solution Overview
Problem
Building a hardware image for a heterogeneous electronic circuit design on a target hardware platform is complex, time-consuming, and error-prone, especially when modules are specified using different programming models, requiring lengthy connectivity graphs and manual script writing.
Innovation Solution
A method and system that automatically generate a hardware image by determining the types of programming models used in a circuit design, generating model-type compiler scripts, and executing a build script to link accelerator representations into a hardware image, thereby simplifying the process and reducing human error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If modules are specified using different programming models and manual scripts are written to compile and link them, then the hardware image can be generated, but the process becomes complex and time-consuming
Solution Approach 1:
The system automatically detects programming models of modules and generates appropriate compiler scripts and build configurations without requiring manual intervention. The toolchain self-adapts to heterogeneous programming models (RTL, behavioral, netlist) and generates the necessary compilation and linking commands, eliminating the need for developers to write manual scripts for each module type.
Solution Approach 2:
The build system is designed to handle multiple programming models and module types through a single unified interface. The system can process RTL modules, behavioral modules, and netlist modules using the same automated workflow, making the hardware image generation process universal across different module specifications rather than requiring separate manual procedures for each type.
2Reliability
If connectivity between modules is manually specified using lengthy connectivity graphs, then the hardware image can be built, but the process becomes error-prone and complex
Solution Approach 1:
The system automatically infers connectivity relationships between modules by analyzing module interfaces and dataflow dependencies. Instead of requiring manual connectivity graph specification, the toolchain self-determines how modules should be connected based on their input/output ports and operational requirements, eliminating manual errors and simplifying the process.
Solution Approach 2:
The manual mechanical process of drawing and specifying connectivity graphs is replaced with an automated algorithmic system that programmatically determines module connections. The system uses software-based analysis of module interfaces and dataflow to automatically generate connectivity specifications, replacing the error-prone manual graphical specification process with a reliable computational approach.
3Reliability
If test bench applications are manually written with compatible datatypes and driver values, then hardware testing can be performed, but additional errors may be introduced
Solution Approach 1:
The system automatically generates test bench applications by analyzing the hardware module specifications and inferred connectivity. The toolchain self-generates appropriate test vectors, driver values, and expected output comparisons based on the module interfaces and operational requirements, eliminating manual test bench creation and reducing the introduction of human errors in test specifications.
Data Source
AI summary
Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications based on one of the types of programming model into an accelerator representation. The design tool can generate a build script configured to execute the compiler scripts and link the accelerator representations into linked accelerator representations. Execution of the build script builds a hardware image from the linked accelerator representations for configuring the programmable IC to implement a circuit according to the circuit design.


