Heterogeneous IC Layout Linking FinFET and GAAFET Transistors
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Solution Overview
Problem
Integrated circuits (ICs) with heterogeneous devices face challenges in optimizing layout area, performance, and heat generation due to the need for multiple devices with different characteristics, requiring effective electrical coupling and design methods to satisfy various requirements.
Innovation Solution
The integration of transistors with distinct structures, such as FinFETs and GAAFETs, connected via specific patterns and connection structures that extend in different directions, allowing for electrical coupling and optimizing performance and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple heterogeneous devices with different optimized characteristics are integrated to satisfy various IC requirements, then performance and area utilization are improved, but device complexity and layout design difficulty increase
Solution Approach 1:
The patent segments the transistor population into homogeneous groups (first plurality of transistors with first characteristics, second plurality with second characteristics) and assigns them to different functional blocks based on specific requirements. This segmentation allows each group to be optimized for its intended function while simplifying the overall design process by treating each group as a manageable unit rather than managing all transistors individually.
Solution Approach 2:
The patent applies local quality by assigning different transistor characteristics to different spatial locations within the IC. Each functional block contains transistors with characteristics locally optimized for that block's specific function, allowing the IC to meet diverse requirements simultaneously while maintaining high performance in each local region.
2Adaptability or versatility
If transistors with different optimized characteristics are used to meet various IC requirements, then adaptability and performance are improved, but manufacturing precision and layout area increase
Solution Approach 1:
The patent divides the transistor population into distinct segments with different characteristics, allowing each segment to be manufactured and laid out with precision tailored to its specific requirements. This segmentation enables the use of different manufacturing parameters for different transistor groups, improving overall manufacturing precision while maintaining adaptability.
Solution Approach 2:
The patent changes key parameters such as channel width, channel length, and gate material across different transistor groups to optimize performance for specific functions. By systematically varying these parameters across different segments, the patent achieves high adaptability while maintaining controllable manufacturing precision through parameterized design rules.
3Speed
If heterogeneous devices are integrated to optimize specific functions, then operating speed and current driving strength are improved, but heat generation and area requirements increase
Solution Approach 1:
The patent applies local quality by placing transistors with high current driving strength and operating speed characteristics in specific functional blocks where high performance is required, while using transistors with lower power consumption characteristics in blocks where speed is less critical. This spatial differentiation of transistor qualities optimizes speed where needed while controlling heat generation in other regions.
Solution Approach 2:
The patent segments the IC into functional blocks with different performance requirements, allowing high-performance transistors to be concentrated in critical paths while lower-power transistors handle less demanding functions. This segmentation enables targeted optimization of speed and heat management rather than uniformly high performance across the entire chip.
Data Source
AI summary
An integrated circuit includes: (i) a first transistor having a first gate extending in a first direction, a first drain, and a first source that is separated from the first drain in a second direction, which is perpendicular to the first direction, (ii) a second transistor having a second gate extending in one of the first and second directions, a second drain, and a second source that is separated from the second drain in a third direction, which is perpendicular to the first and second directions, and (iii) a first connection structure that electrically connects the first transistor to the second transistor, and includes a pattern extending in the first direction between the first transistor and the second transistor.