Heterogeneous IC Package Interposer Design
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Solution Overview
Problem
Conventional multi-chip modules using heterogeneous ICs face challenges with large size, limited signal speeds, and increased costs due to solder bump formation processes in flip-chip bonding, particularly when connecting different types of ICs like semiconductor-based and silicon-based chips.
Innovation Solution
A package structure with a molded package encapsulating an optical chip and a semiconductor chip, utilizing a through-silicon-via structure and redistribution layers to shorten the conductive path, thereby reducing parasitic capacitance and resistance, and eliminating the need for bump formation processes, which includes a molding structure, passivation layers, and conductive structures to connect the chips efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used for conductive connection between heterogeneous ICs, then the multi-chip module can be assembled, but the device size becomes large and signal speeds are limited
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between the optical IC and silicon IC. This interposer provides a common bonding interface (both chips bond to the interposer using the same bump formation process) and enables shorter, lower-inductance connection paths compared to wire bonding, thereby reducing device size while maintaining reliable conductive connection.
2Reliability
If flip-chip bonding with solder bump formation is used to connect different types of ICs, then conductive connection is achieved, but cost increases and overall yield decreases due to multiple different bump formation processes
Solution Approach 1:
The interposer substrate serves as a universal interface that enables both the optical IC and silicon IC to be bonded using the same bump formation process (e.g., all using Cu-Cu or all using Sn-based bumps). This universal approach eliminates the need for multiple different bump formation processes, reducing manufacturing complexity, cost, and improving overall yield.
3Reliability
If conventional multi-chip module assembly is used, then heterogeneous ICs can be connected, but parasitic capacitance and resistance increase due to longer conductive paths
Solution Approach 1:
The interposer architecture transitions from a planar wire-bonding connection to a three-dimensional flip-chip-to-interposer-to-flip-chip structure. This dimensional change enables significantly shorter conductive paths through the vertical stacking arrangement, reducing parasitic capacitance and resistance, and thereby lowering power loss while maintaining electrical connection reliability.
Data Source
AI summary
In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.