Heterogeneous Integration Structure With On-Chip Voltage Regulation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Voltage droop occurs during power delivery to memory devices and accelerators in semiconductor devices due to current paths through through-silicon-vias (TSVs) and other wires, leading to reduced power supply efficiency.

Innovation Solution

Incorporation of voltage regulator modules (VRMs) on top of the chip to regulate power delivery to processors and memory devices, compensating for voltage droop by converting input voltage into operating voltages for accelerators and memory chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If power is delivered through TSVs and wires to memory devices and accelerators, then power supply is achieved, but voltage droop occurs reducing power supply efficiency

Engineering Contradiction:
Improvevoltage droopVSAvoidpower delivery structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent segments the power delivery system by placing individual voltage regulator modules (VRMs) directly on each memory chip and accelerator chip. This segmentation allows each component to have its own dedicated power regulation, eliminating the voltage droop that would otherwise occur through shared TSV and wire paths. Each VRM converts input voltage locally at the component level, ensuring stable power delivery without requiring complex long-distance power transmission infrastructure.

Inventive Principle:
Principle #1Segmentation

2Reliability

If voltage regulator modules are added to regulate power delivery, then voltage droop is reduced, but device complexity increases

Engineering Contradiction:
Improvepower delivery stabilityVSAvoidsemiconductor device structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the voltage regulator module directly with each memory chip and accelerator chip in a coupled arrangement. This merging integrates power conversion functionality into the immediate vicinity of each component, ensuring reliable and stable power delivery. By combining the VRM and the active component into a tightly coupled power delivery system, the patent achieves high reliability without requiring complex external power management infrastructure.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Reduces voltage droop, ensuring stable power delivery to accelerators and memory devices, enhancing overall performance and efficiency of semiconductor devices.

Implementation Method 1

at least one voltage regulator arranged on top of the chip. The at least one voltage regulator can be configured to regulate power being provided from the plurality of TSVs to the processor

Methodology Applied
Scientific EffectVoltage regulation:

Implementation Method 2

a plurality of through-silicon-vias (TSVs). The processor can be configured to communicate with the memory device via a plurality of interconnects

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS12581663B2Heterogeneous integration structure with voltage regulation
Publication Date: 2026.03.17 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12581663B2 patent drawing
  • US12581663B2 patent drawing
  • US12581663B2 patent drawing

AI summary

Heterogeneous integration semiconductor packages with voltage regulation are described. A semiconductor device can include a chip including a memory device and a plurality of through-silicon-vias (TSVs). The semiconductor device can further include a processor arranged on top of the chip. The processor can be configured to communicate with the memory device via a plurality of interconnects. The semiconductor device can further include at least one voltage regulator arranged on top of the chip. The at least one voltage regulator can be configured to regulate power being provided from the plurality of TSVs to the processor.