Heterogeneous Joint Compilation for Fine-Grained Task Division
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Solution Overview
Problem
Existing compilation technologies for heterogeneous hardware architectures struggle to effectively divide and coordinate calculation tasks across different heterogeneous devices, leading to coarse-grained task division and limited compatibility among various compilers, which prevents finer-grained interactions and efficient overall compilation.
Innovation Solution
A joint compilation method and system that determines a strategy for dividing overall calculation tasks into subtasks based on the characteristics of heterogeneous units, allocating these subtasks to corresponding compilers, and linking generated machine instruction codes to form a cohesive set of instructions for the heterogeneous hardware architecture, allowing for automatic coordination and optimization across different hardware units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If coarse-grained task division is used to reduce coordination cost among heterogeneous devices, then device coordination complexity is reduced, but task division fineness and compilation automation are worsened
Solution Approach 1:
The patent divides the overall calculation task into fine-grained subtasks that can be distributed across multiple heterogeneous devices. The compilation system automatically performs this segmentation based on device capabilities, transforming a single complex compilation task into multiple manageable subtasks that can be processed independently by different device compilers.
Solution Approach 2:
The patent introduces a heterogeneous compilation system that acts as an intermediary between the high-level application code and multiple device-specific compilers. This compilation system coordinates task division, manages compiler interactions, and integrates results from different device compilers, enabling fine-grained task division without requiring direct coordination between heterogeneous devices.
2Adaptability or versatility
If multiple heterogeneous device compilers are used to support different hardware architectures, then hardware compatibility is improved, but compilation system complexity and coordination difficulty are worsened
Solution Approach 1:
The patent creates a universal heterogeneous compilation system that can interface with multiple different device compilers (CPU, GPU, DSP, FPGA, ASIC). This compilation system provides a unified interface and coordination mechanism that works across all heterogeneous device types, allowing each device compiler to maintain its specialized functionality while being part of an integrated compilation workflow.
Solution Approach 2:
The patent merges multiple device-specific compilation processes into a single coordinated compilation workflow. The heterogeneous compilation system combines the outputs from various device compilers into a unified executable program, integrating multiple specialized compilation processes while managing their interactions and dependencies.
3Productivity
If fine-grained task division is implemented to enable better hardware utilization, then hardware resource utilization is improved, but coordination overhead and compilation difficulty are worsened
Solution Approach 1:
The patent performs task division and compiler coordination in advance during the compilation phase, before runtime execution. The heterogeneous compilation system pre-processes the application code, divides it into fine-grained subtasks, and prepares the coordination strategy ahead of time. This preliminary action eliminates the need for complex runtime coordination, allowing fine-grained task division without proportionally increasing runtime overhead.
Data Source
AI summary
The present invention provides a joint compilation method and system for a heterogeneous hardware architecture. The method comprises steps of: determining, according to calculation characteristics of heterogeneous units in the hardware architecture, a strategy for dividing an overall calculation task graph into a plurality of subtasks, and allocating the plurality of divided subtasks to corresponding heterogeneous unit compilers for compilation to generate corresponding target machine instruction codes; and, linking the generated target machine instruction codes to form a set of machine instruction codes oriented to the heterogeneous hardware architecture. With the joint compilation method and system of the present invention, an executable program body, which can run on a heterogeneous hardware architecture system and be mixed with hardware machine instruction codes of various heterogeneous units at different levels, can be automatically compiled, optimized and generated by activating one compilation.